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march 2008 rev 4 1/123 1 m58pr512le M58PR001LE 512-mbit or 1-gbit ( 16, multiple bank, multilevel, burst) 1.8 v supply flash memories features supply voltage ?v dd = 1.7 v to 2.0 v for program, erase and read ?v ddq = 1.7 v to 2.0 v for i/o buffers ?v pp = 9 v for fast program synchronous/asynchronous read ? synchronous burst read mode: 108 mhz, 66 mhz ? asynchronous page read mode ? random access: 96 ns programming time ? 4.2 s typical word program time using buffer enhanced factory program command memory organization ? multiple bank memory array: 64 mbit banks (512 mb devices) 128 mbit banks (1 gb devices) ? four efa (extended flash array) blocks of 64 kbits dual operations ? program/erase in one bank while read in others ? no delay between read and write operations block locking ? all blocks locked at power-up ? any combination of blocks can be locked with zero latency ?wp for block lock-down ? absolute write protection with v pp = v ss security ? 64 bit unique device number ? 2112 bit user programmable otp cells cfi (common flash interface) 100 000 program/erase cycles per block electronic signature ? manufacturer code: 20h ? 512 mbit device: 8819 ? 1 gbit device: 880f ecopack? package available. fbga tfbga105 (zad) 9 x 11 mm tfbga107 (zac) 8 x 11 mm www.numonyx.com
contents m58pr512le, M58PR001LE 2/123 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1 address inputs (a0-amax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 data inputs/outputs (dq0-dq15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 chip enable (e ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4 output enable (g ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5 write enable (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6 write protect (wp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7 reset (rp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.8 deep power-down (dpd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.9 latch enable (l ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.10 clock (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.11 wait (wait) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.12 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.13 v ddq supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.14 v pp program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.15 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.16 v ssq ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 address latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.7 deep power-down (dpd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 read array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 read status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
m58pr512le, M58PR001LE contents 3/123 4.3 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4 read cfi query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5 clear status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.6 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.7 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.8 buffer program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.9 buffer enhanced factory program command . . . . . . . . . . . . . . . . . . . . . 29 4.9.1 setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.9.2 program and verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.9.3 exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.10 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.11 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.12 protection register program command . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.13 set configuration register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.14 block lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.15 block unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.16 block lock-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.17 blank check command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.18 set enhanced configuration register command . . . . . . . . . . . . . . . . . . . 35 4.19 read efa block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.20 program efa block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.21 erase efa block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.22 suspend efa block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.23 resume efa block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.24 lock efa block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.25 unlock efa block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.26 lock-down efa block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5 program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.1 program regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.2 program modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.2.1 control program mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.2.2 object program mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3 program methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
contents m58pr512le, M58PR001LE 4/123 5.3.1 single word program method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3.2 buffer program method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3.3 buffer enhanced factory program method . . . . . . . . . . . . . . . . . . . . . . . 47 6 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1 control program mode status bit (sr9) . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.2 object program mode status bit (sr8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3 program/erase controller status bit (sr7) . . . . . . . . . . . . . . . . . . . . . . . . 49 6.4 erase suspend status bit (sr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.5 erase status bit (sr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.6 program status bit (sr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.7 v pp status bit (sr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.8 program suspend status bit (sr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.9 block protection status bit (sr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.10 bank write/multiple word program status bit (sr0) . . . . . . . . . . . . . . . . . 51 7 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.1 read select bit (cr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.2 x latency bits (cr14-cr11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.3 wait polarity bit (cr10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.4 wait configuration bit (cr8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.5 burst length bits (cr2-cr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8 enhanced configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.1 deep power-down mode bit (ecr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.2 deep power-down polarity bit (ecr14) . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.3 output driver control bits (ecr2-ecr0) . . . . . . . . . . . . . . . . . . . . . . . . . 58 9 extended flash array (efa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10 read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.1 asynchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.2 synchronous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.3 single synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
m58pr512le, M58PR001LE contents 5/123 11 dual operations and multiple bank architectu re . . . . . . . . . . . . . . . . . 63 12 block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.1 reading a block?s lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.2 locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.3 unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.4 lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.5 locking operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . . . 66 13 program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 68 14 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 15 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 16 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 17 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 appendix a block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 appendix b common flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 appendix c flowcharts and pseudocodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 appendix d command interface state ta bles. . . . . . . . . . . . . . . . . . . . . . . . . . . 115 18 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
list of tables m58pr512le, M58PR001LE 6/123 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2. m58pr512le bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 table 3. M58PR001LE bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 table 4. efa memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 5. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6. command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 7. standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 8. factory program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 9. electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 10. protection register locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 11. program methods available with each program mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 12. relationships between program methods and program modes . . . . . . . . . . . . . . . . . . . . . 47 table 13. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 14. x latency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 15. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 16. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 17. enhanced configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 18. dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 table 19. dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 20. dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 21. lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 22. program/erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 23. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 24. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 25. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 26. dc characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 27. dc characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 28. asynchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 29. synchronous read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 0 table 30. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 31. write ac characteristics, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 32. reset and power-up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 33. deep power-down ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 34. tfbga105 9 11 mm - 9 12 active ball array, 0.8 mm pitch, mechanical data . . . . . . . 88 table 35. stacked tfbga107 8 11 mm - 9 12 active ball array, 0.8 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 36. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 37. m58pr512le - bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 38. M58PR001LE - bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 39. m58pr512le - block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 table 40. M58PR001LE - block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 table 41. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 42. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 43. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 table 44. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 45. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 46. protection register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 47. burst read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
m58pr512le, M58PR001LE list of tables 7/123 table 48. bank and erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 49. bank and erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 50. extended flash array bank and erase block region information . . . . . . . . . . . . . . . . . . . . 103 table 51. extended flash array bank and erase block region 1 information . . . . . . . . . . . . . . . . . . . 104 table 52. command interface states - modify table, next state 1. . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 53. command interface states - modify table, next state 2. . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 54. command interface states - modify table, next output 1 . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 55. command interface states - modify table, next output 2 . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 56. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
list of figures m58pr512le, M58PR001LE 8/123 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. tfbga105 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3. tfbga107 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5. main array architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. protection register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 7. program regions configured in control or object program mode. . . . . . . . . . . . . . . . . . . . . 45 figure 8. x latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 9. wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 10. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 11. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 12. asynchronous random access read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 13. asynchronous page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 14. synchronous burst read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 15. single synchronous read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 16. clock input ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 17. write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 18. write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 19. reset and power-up ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 20. deep power-down ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 21. reset during deep power-down ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 22. tfbga105 9 11 mm - 9 12 active ball array, 0.8 mm pitch, package outline. . . . . . . . 87 figure 23. tfbga107 8 11 mm - 9 12 active ball array, 0.8 mm pitch, package outline. . . . . . . . 88 figure 24. program and efa block program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . 106 figure 25. buffer program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 26. program suspend and resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . 108 figure 27. block erase and efa block erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . 109 figure 28. erase suspend and resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 29. main array and efa locking operations flowchart and pseudocode . . . . . . . . . . . . . . . . . 111 figure 30. blank check flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 31. protection register program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 32. buffer enhanced factory program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . 114
m58pr512le, M58PR001LE description 9/123 1 description the m58pr512le and M58PR001LE are 512 mbit (32 mbit x 16) and 1 gbit (64 mbit x 16) non-volatile flash memories. they are collectively referred to as the m58prxxxle in the rest of the document, unless otherwise specified. the m58prxxxle may be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.7 v to 2.0 v v dd supply for the circuitry and a 1.7 v to 2.0 v v ddq supply for the input/output pins. an optional 9 v v pp power supply is provided to speed up factory programming. the m58prxxxle has a uniform block architecture and is based on a multilevel cell technology: the m58pr512le has an array of 256 blocks, and is divided into 64 mbit banks. there are 8 banks each containing 32 blocks of 128 kwords. the M58PR001LE has an array of 512 blocks, and is divided into 128 mbit banks. there are 8 banks each containing 64 blocks of 128 kwords. each block contains 256 program regions of 1 kbyte each, that are divided into 32 segments of 16 words. each segment is split into two halves (a and b), according by the value on address input a3. the memory map is illustrated in figure 4 and the main array architecture in figure 5 . the multiple bank architecture allows dual operations. while programming or erasing in one bank, read operations are possible in other banks. only one bank at a time is allowed to be in program or erase mode. it is possible to perform burst reads that cross bank boundaries. the bank architectures are summarized in ta b l e 2 and ta bl e 3 , and the memory maps are shown in figure 4 and . each block can be erased separately. erase can be suspended to perform a program or read operation in any other block, and then resumed. program can be suspended to read data at any memory location except for the one being programmed, and then resumed. each block can be programmed and erased over 100 000 cycles using the supply voltage v dd . there is a buffer enhanced factory programming command available to speed up programming. program and erase commands are written to the command interface of the memory. an internal program/erase controller takes care of the timings necessary for program and erase operations. the end of a program or erase operation can be detected and any error conditions identified in the status register. the command set required to control the memory is consistent with jedec standards. the device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. in synchronous burst read mode, data is output on each clock cycle at frequencies of up to 108 mhz. the device features an automatic standby mode and deep power-down mode. when the bus is inactive during asynchronous read operations, the device automatically switches to automatic standby mode. in this state the power consumption is reduced to the standby value and the outputs are still driven. the dpd (deep power-down) mode starts when the device is properly configured (ecr bit 15 is set) and the dpd signal is asserted. in dpd mode the device has the lowest power consumption.
description m58pr512le, M58PR001LE 10/123 the m58prxxxle features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. all blocks have three levels of protection. they can be locked and locked-down individually preventing any accidental programming or erasure. there is an additional hardware protection against program and erase. when v pp v pplk all blocks are protected against program or erase. all blocks are locked at power-up. in addition to the main memory array, the m58prxxxle features an extended flash array (efa) divided into 4 blocks of 64 kbits each. the efa blocks are accessed through a separate set of commands. the operations available in the efa blocks are asynchronous read (in non-page mode), single word program, erase and block locking. see section 4: command interface for details of the efa commands set. see ta bl e 4 for an extended flash array memory map. ta bl e 1 8 and ta b l e 1 9 describe the simultaneous operations allowed in the efa blocks and the main memory array. the device includes 17 protection registers and 2 protection register locks, one for the first protection register and the other for the 16 otp (one-time-programmable) protection registers of 128 bits each. the first protection r egister is divided into two areas: a 64-bit area containing a unique device number written by st, and a 64-bit area one-time-programmable by the user. the user programmable area can be permanently protected. figure 6 , shows the protection register memory map. the memory is available in tfbga105 or tfbga107 packages, and is supplied with all the bits erased (set to ?1?). figure 1. logic diagram 1. amax is equal to a24 in the m58pr512le and to a25 in the M58PR001LE. ai12816c a0-amax (1) w dq0-dq15 v dd m58pr512le M58PR001LE e v ss 16 g rp wp v ddq v pp l k wait v ssq dpd
m58pr512le, M58PR001LE description 11/123 table 1. signal names signal name function direction a0-amax (1) 1. amax is equal to a24 in the m58pr512le and to a25 in the M58PR001LE. address inputs inputs dq0-dq15 data input/outputs, command inputs i/o e chip enable input g output enable input w write enable input rp reset input wp write protect input k clock input l latch enable input wait wait output dpd deep power-down input v dd supply voltage v ddq supply voltage for input/output buffers v pp optional supply voltage for fast program and erase v ss ground v ssq ground input/output supply du do not use nc not connected
description m58pr512le, M58PR001LE 12/123 figure 2. tfbga105 connections (top view through package) 1. ball a8 is a25 in the m58pr0001le and it is not connected internally (nc) in the m58pr512le. 8 7 6 5 4 3 2 1 c b a22 a2 nc d e f du a4 a17 a5 a3 a1 v ss a0 v ddf nc a21 nc a8 nc a20 nc a10 nc nc nc nc nc nc nc dq2 dq11 dq9 dq1 dq12 dq7 dq6 dq5 dq3 a24 a25/ nc (1) dq0 du dq15 nc a g h j k ai10 9 nc l m a18 dpd f l f nc v ddq a9 9 a16 a11 a15 a14 a13 dq13 dq14 du du nc wait f a12 a6 a7 a19 a23 v ss v ss nc v ss v ss v ss nc v ddf nc nc wp f w f nc nc nc nc e f nc rp f g f v ppf v ddq v ddq v ddf v ddf v ddq v ss v ss v ss k f v ss v ss v ss dq10 dq8 dq4 nc nc nc nc
m58pr512le, M58PR001LE description 13/123 figure 3. tfbga107 connections (top view through package) 1. ball e4 is a25 in the m58pr0001le and is not connected internally (nc) in the m58pr512le. ai11098d nc dq14 dq0 a16 wait dq13 dq8 h dq7 d c a17 a22 b a21 a 8 7 6 5 4 3 2 1 a5 a3 g f e a1 du k a7 a2 a8 nc a11 nc a13 du 9 a4 a12 m l k j dq15 v ss nc du nc dq6 nc du dq12 l nc dq4 dq10 v ss v ppf a18 v ss dq11 dq1 a23 a24 a19 nc du dq9 a14 nc a20 v ddf dq3 dq5 dq2 a6 du du du du nc nc du nc nc nc nc dpd f v ss nc v ss nc v ss v ss v ddq v ddq du du du nc nc a9 wp f a10 a15 nc rp f w f nc a0 nc e f g f nc v ddq nc v ss v ddq v ddf v ss v ss v ss v ss a25/ nc (1)
description m58pr512le, M58PR001LE 14/123 table 2. m58pr512le bank architecture number bank size blocks bank 0 64 mbits 32 blocks of 128 kwords bank 1 64 mbits 32 blocks of 128 kwords bank 2 64 mbits 32 blocks of 128 kwords ---- ---- ---- bank 7 64 mbits 32 blocks of 128 kwords table 3. M58PR001LE bank architecture number bank size blocks bank 0 128 mbits 64 blocks of 128 kwords bank 1 128 mbits 64 blocks of 128 kwords bank 2 128 mbits 64 blocks of 128 kwords ---- ---- ---- bank 7 128 mbits 64 blocks of 128 kwords
m58pr512le, M58PR001LE description 15/123 figure 4. memory map table 4. efa memory map efa block size address range 3 4 kwords (64 kbits) 0003000 - 0003fff 2 4 kwords (64 kbits) 0002000 - 0002fff 1 4 kwords (64 kbits) 0001000 - 0001fff 0 4 kwords (64 kbits) 0000000 - 0000fff ai12817c m58pr512le address lines a24-a0 128 kword 0000000h 001ffffh 128 kword 03e0000h 03fffffh 128 kword 1c00000h 1c1ffffh 128 kword 1fe0000h 1ffffffh bank 7 bank 0 32 blocks 32 blocks M58PR001LE address lines a25-a0 128 kword 0000000h 001ffffh 128 kword 07e0000h 07fffffh 128 kword 3800000h 381ffffh 128 kword 3fe0000h 3ffffffh bank 7 bank 0 64 blocks 64 blocks
description m58pr512le, M58PR001LE 16/123 figure 5. main array architecture . . . 128 kword block 128 kword block . . . 128 kword block bank 0 bank 7 512 mbits or 1 gbits . . . main array program region 0 512 words program region 1 512 words program region 255 512 words program region 254 512 words . . . . . . segment 31 - 16 words ai12886b block segment 0 - 16 words segment 1 - 16 words segment 2 - 16 words segment 30 - 16 words program region 128 kword block
m58pr512le, M58PR001LE signal descriptions 17/123 2 signal descriptions see figure 1: logic diagram and table 1: signal names for a brief overview of the signals connected to this device. 2.1 address inputs (a0-amax) amax is the highest order address input. amax is a24 in the m58pr512le and a25 in the M58PR001LE. the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the program/erase controller. 2.2 data inputs/outputs (dq0-dq15) the data i/o output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a bus write operation. 2.3 chip enable (e ) the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip enable is at v il and reset is at v ih the device is in active mode. when chip enable is at v ih the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. 2.4 output enable (g ) the output enable input controls data outputs during the bus read operation of the memory. 2.5 write enable (w ) the write enable input controls the bus write operation of the memory?s command interface. the data and address inputs are latched on the rising edge of chip enable or write enable, whichever occurs first. 2.6 write protect (wp ) write protect is an input that gives an additional hardware protection for each block. when write protect is at v il , the lock-down is enabled and the protection status of the locked- down blocks cannot be changed. when write protect is at v ih , the lock-down is disabled and the locked-down blocks can be locked or unlocked (refer to table 21: lock status ).
signal descriptions m58pr512le, M58PR001LE 18/123 2.7 reset (rp ) the reset input provides a hardware reset of the memory. when reset is at v il , the memory is in reset mode, this means the outputs are high impedance and the current consumption is reduced to the reset supply current i dd2 . refer to ta b l e 2 6 : d c characteristics - currents for the value of i dd2 . after reset, all blocks are in the locked state and the configuration register is reset. when reset is at v ih , the device is in normal operation. exiting reset mode the device enters asynchronous read mode, but a negative transition of chip enable or latch enable is required to ensure valid data outputs. the reset pin can be interfaced with 3 v logic without any additional circuitry, and can be tied to v rph (refer to table 27: dc characteristics - voltages ). 2.8 deep power-down (dpd) the deep power-down input is used to put the device in deep power-down mode. when the device is in standby mode and the enhanced configuration register bit ecr15 is set, asserting the deep power-down input will cause the memory to enter the deep power- down mode. when the device is in the deep power-down mode, the memory cannot be modified and the data is protected. the polarity of the dpd pin is determined by ecr14. the deep power-down input is active low by default. 2.9 latch enable (l ) latch enable latches the address bits on its rising edge. the address latch is transparent when latch enable is at v il and it is inhibited when latch enable is at v ih . latch enable can be kept low (also at board level) when the latch enable function is not required or supported. 2.10 clock (k) the clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a clock edge when latch enable is at v il . clock is ignored during asynchronous read and in write operations. 2.11 wait (wait) wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. this output is high impedance when chip enable is at v ih , output enable is at v ih , or reset is at v il . it can be configured to be active during the wait cycle or one data cycle in advance.
m58pr512le, M58PR001LE signal descriptions 19/123 2.12 v dd supply voltage v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). 2.13 v ddq supply voltage v ddq provides the power supply to the i/o pins and enables all outputs to be powered independently of v dd . v ddq can be tied to v dd or can use a separate supply. v ddq is sampled at the beginning of program/erase operations. if v ddq is lower than v lkoq , the device is reset. 2.14 v pp program supply voltage v pp is both a control input and a power supply pin. the two functions are selected by the voltage range applied to the pin. if v pp is kept in a low voltage range (0 v to v ddq ) v pp is seen as a control input. in this case a voltage lower than v pplk gives an absolute protection against program or erase, while v pp > v pp1 enables these functions (see tables 26 and 27 , dc characteristics for the relevant values). v pp is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. if v pp is in the range of v pph it acts as a power supply pin. in this condition v pp must be stable until the program/erase algorithm is completed. 2.15 v ss ground v ss ground is the reference for the core supply. it must be connected to the system ground. 2.16 v ssq ground v ssq ground is the reference for the input/output circuitry driven by v ddq . v ssq must be connected to v ss . note: each device in a system should have v dd , v ddq and v pp decoupled with a 0.1 f ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). see figure 11: ac measurement load circuit . the pcb track widths should be sufficient to carry the required v pp program and erase currents.
bus operations m58pr512le, M58PR001LE 20/123 3 bus operations there are seven standard bus operations that control the device. these are bus read, bus write, address latch, output disable, standby, reset and deep power-down. see ta b l e 5 : bus operations , for a summary. typically glitches of less than 5 ns on chip enable or write enable are ignored by the memory and do not affect bus write operations. 3.1 bus read bus read operations are used to output the contents of the memory array, the electronic signature, the status register and the common flash interface. both chip enable and output enable must be at v il in order to perform a read operation. the chip enable input should be used to enable the device. output enable should be used to gate data onto the output. the data read depends on the previous command written to the memory (see section 4: command interface ). see figures 12 , 13 , 14 and 15 , read ac waveforms, and tables 28 and 29 , read ac characteristics, for details of when the output becomes valid. 3.2 bus write bus write operations write commands to the memory or latch input data to be programmed. a bus write operation is initiated when chip enable and write enable are at v il with output enable at v ih . commands, input data and addresses are latched on the rising edge of write enable or chip enable, whichever occurs first. the addresses can also be latched prior to the write operation by toggling latch enable. in this case the latch enable should be tied to v ih during the bus write operation. see figures 17 and 18 , write ac waveforms, and tables 30 and 31 , write ac characteristics, for details of the timing requirements. 3.3 address latch address latch operations input valid addresses. both chip enable and latch enable must be at v il during address latch operations. the addresses are latched on the rising edge of latch enable. 3.4 output disable the outputs are high impedance when the output enable is at v ih .
m58pr512le, M58PR001LE bus operations 21/123 3.5 standby standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. the memory is in standby when chip enable and reset are at v ih . the power consumption is reduced to the standby level i dd3 and the outputs are set to high impedance, independently from the output enable or write enable inputs. if chip enable switches to v ih during a program or erase operation, the device enters standby mode when finished. 3.6 reset during reset mode the memory is deselected and the outputs are high impedance. the memory is in reset mode when reset is at v il . the power consumption is reduced to the reset level, independently from the chip enable, output enable or write enable inputs. if reset is pulled to v ss during a program or erase, this operation is aborted and the memory content is no longer valid. 3.7 deep power-down (dpd) the memory enters the deep power-down mode from the standby mode (rp and e are de- asserted, v ih ) by setting ecr15 high (set to ?1?) and asserting the dpd pin (these two events can be done in any order). the dpd pin polarity is determined by the value of ecr14 when: ecr14 is cleared (?0?) the dpd pin is active low. the dpd pin is active low by default. ecr14 is set (?1?), the dpd pin is active high. while in dpd mode, the: values of the configuration register, enhanced configuration register, block lock bits, and bank states are preserved. status register is reset to 80h. if the status register contains errors before entering the dpd mode, the error bits are lost after exiting dpd mode. the device should not be put in deep power-down mode while a program, erase or suspend operation is in progress, otherwise the operation aborts, and the memory contents are no longer valid. the deep power-down mode is exited t dphel after de-asserting the dpd pin. upon exiting the deep power-down mode, the memory reverts to standby mode. if the rp pin is asserted while in dpd mode , the device exits dpd mode after t phel and ecr15 is reset to 0.
bus operations m58pr512le, M58PR001LE 22/123 table 5. bus operations (1) 1. x = don't care. operation e g w l rp dpd (2) 2. the dpd signal polarity depends on the value of the ecr14 bit. wait (3) 3. wait signal polarity is configured us ing the set configuration register command. dq15-dq0 bus read v il v il v ih v il (4) 4. l can be tied to v ih if the valid address has been previously latched. v ih de- asserted (5) 5. if ecr15 is set to '0', the device cannot enter the deep power-down mode, even if dpd is asserted. data output bus write v il v ih v il v il (4) v ih de- asserted (5) data input address latch v il xv ih v il v ih de- asserted (5) data output or hi-z (6) 6. depends on g . output disable v il v ih v ih xv ih de- asserted (5) hi-z hi-z standby v ih xx x v ih de- asserted (5) hi-z hi-z reset x x x x v il de- asserted (5) hi-z hi-z deep power- down v ih xx x v ih asserted (7) 7. ecr15 has to be set to ?1? for the device to enter deep power-down. hi-z hi-z
m58pr512le, M58PR001LE command interface 23/123 4 command interface all bus write operations to the memory are interpreted by the command interface. commands consist of one or more sequential bus write operations. an internal program/erase controller handles all timings and verifies the correct execution of the program and erase commands. the program/erase controller provides a status register, whose output may be read at any time to monitor the progress or the result of the operation. the command interface is reset to read mode when power is first applied, when exiting from reset, or whenever v dd is lower than v lko . command sequences must be followed precisely. any invalid combination of commands are ignored. refer to table 6: command codes , table 7: standard commands , table 8: factory program command for a summary of the command interface. table 6. command codes hex code command 01h block lock confirm and efa block lock confirm 03h set configuration register confirm 04h set enhanced configuration register confirm 20h block erase setup 24h efa block erase setup 2fh block lock-down confirm and efa block lock-down confirm 41h program setup 44h efa program setup 50h clear status register 60h block lock setup, block unlock setup, block lock-down setup, set configuration register setup and enhanced configuration register setup 64h efa block lock, efa block lock-down, efa block unlock 70h read status register 80h buffer enhanced factory program 90h read electronic signature 94h read efa 98h read cfi query b0h program/erase suspend bch blank check setup c0h protection register program d0h program/erase resume, block erase confirm, block unlock confirm or buffer program confirm, buffer enhanced factor y program confirm, blank check confirm, unlock efa block confirm, efa block erase confirm e9h buffer program ffh read array
command interface m58pr512le, M58PR001LE 24/123 4.1 read array command the read array command returns the addressed bank to read array mode. one bus write cycle is required to issue the read array command. once a bank is in read array mode, subsequent read operations output the data from the memory array. a read array command can be issued to any banks while programming or erasing in another bank. if the read array command is issued to a bank currently executing a program or erase operation, the bank returns to read array mode but the program or erase operation continues. however, the data output from the bank is not guaranteed until the program or erase operation has finished. the read modes of other banks are not affected. 4.2 read status register command the device contains a status register th at monitors program or erase operations. the read status register command reads the contents of the status register for the addressed bank. one bus write cycle is required to issue the r ead status register command. once a bank is in read status register mode, subsequent read operations output the contents of the status register. the status register data is la tched on the falling edge of the chip enable or output enable signals. either chip enable or output enable must be toggled to update the status register data. the read status register command can be issued at any time, even during program or erase operations. the read status register command only changes the read mode of the addressed bank. the read modes of other banks are not affected. only asynchronous read and single synchronous read operations should be used to read the status register. a read array command is required to return the bank to read array mode. see ta bl e 1 3 for the description of the status register bits.
m58pr512le, M58PR001LE command interface 25/123 4.3 read electronic signature command the read electronic signature command reads the manufacturer and device codes, the lock status of the addressed bank, the protec tion register, the configuration register, and the enhanced configuration register. one bus write cycle is required to issue the read electronic signature command. once a bank is in read electronic signature mode, subsequent read operations in the same bank output the manufacturer code, the device code, the lock status of the addressed bank, the protection register, the configuration register, or the enhanced configuration register (see ta bl e 9 ). the read electronic signature command can be issued at any time, even during program or erase operations, except during protection register program operations. dual operations between the efa and the electronic signature locations are not allowed (see table 20: dual operation limitations for details). if a read electronic signature command is issu ed to a bank that is executing a program or erase operation the bank goes into read el ectronic signature mode. subsequent bus read cycles output the electronic signature data and the program/erase controller continues to program or erase in the background. the read electronic signature command only changes the read mode of the addressed bank. the read modes of other banks are not affected. only asynchronous read and single synchronous read operations should be used to read the electronic signature. a read array command is required to return the bank to read array mode. 4.4 read cfi query command the read cfi query command is used to read data from the cfi (common flash interface). one bus write cycle is required to issue the read cfi query command. once a bank is in read cfi query mode, subsequent bus read operations in the same bank output the contents of the cfi. the read cfi query command can be issued at any time, even during program or erase operations. if a read cfi query command is issued to a bank that is executing a program or erase operation the bank goes into read cfi query mode. subsequent bus read cycles output the cfi data and the program/erase controller continues to program or erase in the background. the read cfi query command only changes the read mode of the addressed bank. the read modes of other banks are not affected. only asynchronous read and single synchronous read operations should be used to read from the cfi. a read array command is required to return the bank to read array mode. dual operations between the efa and the cfi memory space are not allowed (see ta b l e 2 0 : dual operation limitations for details).
command interface m58pr512le, M58PR001LE 26/123 4.5 clear status register command the clear status register command can be used to reset (set to ?0?) all error bits (sr1, sr3, sr4, sr5, sr8 and sr9) in the status register. one bus write cycle is required to issue the clear status register command. the clear status register command does not affect the read mode of the bank. the error bits in the status register do not automatically return to ?0? when a new command is issued. the error bits in the status register should be cleared before attempting a new program or erase command. 4.6 block erase command the block erase command erases a block. it sets all the bits within the selected block to ?1?, and all previous data in the block is lost. if the block is protected then the erase operation aborts, the data in the block is not changed, and the status register outputs the error. two bus write cycles are required to issue the command. the first bus cycle sets up the block erase command. the second latches the block address and starts the program/erase controller. if the second bus cycle is not the block erase confirm code, status register bits sr4 and sr5 are set and the command is aborted. once the command is issued, the bank enters read status register mode and any read operation within the addressed bank outputs the contents of the status register. a read array command is required to return the bank to read array mode. during block erase operations the bank containing the block being erased only accepts the read array, read status register, read electronic signature, read cfi query and the program/erase suspend command; all other commands are ignored. the block erase operation aborts if reset, rp , goes to v il . as data integrity cannot be guaranteed when the block erase operation is aborted, the block must be erased again. refer to chapter 11 for detailed information about simultaneous operations allowed in banks not being erased. typical erase times are provided in table 22: program/erase times and endurance cycles . see appendix c , figure 27: block erase and efa bloc k erase flowchart and pseudocode for a suggested flowchart for using the block erase command.
m58pr512le, M58PR001LE command interface 27/123 4.7 program command the program command programs a single word to the memory array. it is supported only by program regions configured in control program mode. if a program command is issued to a program region configured in object program mode, the program operation is aborted and the sr4 and sr8 status register bits are set (see section 5: program operations ). two bus write cycles are required to issue the program command. the first bus cycle sets up the program command. the second latches the address and data to be programmed and starts the p/ec (program/erase controller). the program command has to be written to the ?a? segment halves (address bit a3 = 0) in the 1 kbyte program region, whereas the data to be programmed is written to the specific address of the bank to be programmed. once the programming has started, read operations in the bank being programmed output the status register contents. programming can be performed in one bank at a time, meanwhile the other banks must be in read or erase suspend mode. the status register p/ec bit, sr7, indicates the progress of the program operation. it should be read to check whether the operation has completed or not. after completion of the program operation (sr7 = 1), one of the error bits (sr4, sr3 and sr1) going high means that an error was detecte. either a failure occurred during programming, v pp is outside the allowed voltage range, or an attempt to program a locked block was made. see section 6: status register for detailed information. during a program operation, the bank containing the word being programmed only accepts the read array, read status register, read electronic signature, read cfi query and the program/erase suspend command; all other commands are ignored. a read array command is required to return the bank to read array mode. refer to chapter 11 for detailed information about simultaneous operations allowed in banks not being programmed. typical program times are given in table 22: program/erase times and endurance cycles . the program operation aborts if reset, rp , goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the word must be reprogrammed. see appendix c , figure 24: program and efa block program flowchart and pseudocode for the flowchart for using the program command.
command interface m58pr512le, M58PR001LE 28/123 4.8 buffer program command the buffer program command uses the device?s 1 kbyte write buffer to speed up programming. up to 1 kbyte can be loaded into the write buffer and programmed into the specified 1 kb aligned location in the main array. the buffer program command dramatically reduces in-system programming time compared to the standard non-buffered program command. the buffer program command is supported in both object program mode and control program mode. when using the buffer program command in a region configured in object mode, the start programming address must be aligned to the 1 kb buffer. when using the buffer program command in a region configured in control program mode, the programmed address must be within the ?a? segment halves of the program region (addresses with a3 = 0) and the ?b? segment halves of the program region (addresses with a3 = 1) must be filled only with ffffh data. before issuing the buffer program setup command, the status register bit sr7 at the bank address should be read to ensure that the buffer is available (sr7=1). four successive steps are required to issue the buffer program command: 1. the first bus write cycle sets up the buffer program command. the setup code can be addressed to any location within the targeted block. 2. the second bus write cycle sets up the number of words to be programmed. value n is written to the same block address, where n+1 is the number of words to be programmed. the maximum buffer count is 1ff (512 words). 3. use n+1 bus write cycles to load the address and data for each word into the write buffer. addresses must lie within the range from the start address to the start address + n, where the start address is the location of the first data to be programmed. the start address must be aligned to a 1 kb boundary. 4. the final bus write cycle confirms the buffer program command and starts the program operation. all the addresses used in the buffer program operation must lie within the same block. the buffer program operation does not change the read status of the banks until the buffer program confirm command is issued. the buffer program confirm command changes the read status of the bank to read status register, therefore, after the buffer program confirm command, read operations in the bank output the contents of the status register. invalid address combinations or failure to fo llow the correct sequence of bus write cycles sets an error in the status register and aborts the operation without affecting the data in the memory array. if the block being programmed is protected, an error is set in the status register and the operation aborts without affecting the data in the memory array. during buffer program operations the bank being programmed only accepts the read array, read status register, read electronic signature, read cfi query and the program/erase suspend commands; all other commands are ignored. refer to chapter 11 for detailed information about simultaneous operations allowed in banks not being programmed. see appendix c , figure 25: buffer program flowchart and pseudocode for a suggested flowchart on using the buffer program command.
m58pr512le, M58PR001LE command interface 29/123 4.9 buffer enhanced factory program command the buffer enhanced factory program command has been specially developed to speed up programming in manufacturing environments where programming time is critical. this command programs one or more write buffer(s) of 1 kb to an aligned 1 kb program region. once the device enters buffer enhanced factory program mode, the write buffer can be reloaded any number of times as long as the address remains within the same main array block. only one block can be programmed at a time. when programming a program region configured in control program mode with the buffer enhanced factory program command, the ?b? half segment addresses (a3 = 1) should not contain ?0? values. when writing to a program region configured in object program mode, the b half may contain some ?0? values. if the number of bytes to program is less than 1 kbyte, the remaining addresses must be filled with ffffh. the use of the buffer enhanced factory program command requires the following operating conditions: v pp must be set to v pph v dd must be within operating range ambient temperature t a must be 30 c 10 c the targeted block must be unlocked the start address must be aligned with the start of a 1 kb buffer boundary the address must remain the start address throughout programming. dual operations are not supported during the buffer enhanced factory program operation, and the command cannot be suspended. the buffer enhanced factory command programs one block at a time. all data to be programmed must be contained in a single block. if the internal address counter is incremented beyond the highest block address, addressing wraps around to the beginning of the block. the buffer enhanced factory program command consists of three phases: the setup phase, the program and verify phase, and the exit phase (please refer to ta b l e 8 : fa c t o r y program command for detailed information). 4.9.1 setup phase the buffer enhanced factory program command requires two bus write cycles to initiate the command. the first bus write cycle sets up the buffer enhanced factory program command. the second bus write cycle confirms the command. after the confirm command is issued, read operations output the contents of the status register. the read status register command must not be issued or it is interpreted as data to program. the status register p/ec bit sr7 should be re ad to check that the p/ec is ready to proceed to the next phase. if an error is detected, sr4 goes high (set to ?1?) and the buffer enhanced factory program operation is terminated. see chapter 6: status register for details on the error.
command interface m58pr512le, M58PR001LE 30/123 4.9.2 program an d verify phase the program and verify phase requires 512 cycles to program the 512 words to the write buffer. the data is stored sequentially, starting at the first address of the write buffer, until the write buffer is full (512 words). to program less than 512 words, the remaining words should be programmed with ffffh. three successive steps are required to issue and execute the program and verify phase of the command. 1. use one bus write operation to latch the start address and the first word to be programmed. the status register bank write status bit sr0 should be read to check that the p/ec is ready for the next word. 2. each subsequent word to be programmed is latched with a new bus write operation. the address must remain the start address as the p/ec increments the address location. if any address is given that is not in the same block as the start address, the program and verify phase terminates. status register bit sr0 should be read between each bus write cycle to check the p/ec is ready for the next word. 3. once the write buffer is full, the data is programmed sequentially to the memory array. after the program operation the device automatically verifies the data and reprograms if necessary. the program and verify phase can be repeated, without re-issuing the command, to program additional 512 word locations as long as the address remains in the same block. 4. finally, after all words, or the entire block have been programmed, write ffffh to any address outside the block containing the start address to terminate the program and verify phase. status register bit sr0 must be checked to determine whether the program operation is finished. the status register may be checked fo r errors at any time but it must be checked after the entire block has been programmed. 4.9.3 exit phase when status register p/ec bit sr7 is set to ?1? this indicates that the device has exited the buffer enhanced factory program operation. upon exiting the buffered enhanced factory program algorithm by writing ffffh to an address outside the block containing the start address, the read mode of the programmed and addressed banks remains unchanged. a full status register check should be done to ensure that the block has been successfully programmed. see chapter 6: status register for more details. for optimum performance the buffer enhanced factory program command should be limited to a maximum of 100 program/erase cycles per block. if this limit is exceeded the internal algorithm continues to work properly but some degradation in performance is possible. typical program times are provided in ta bl e 2 2 . see appendix c , figure 32: buffer enhanced factory program flowchart and pseudocode for a suggested flowchart on using the buffer enhanced factory program command.
m58pr512le, M58PR001LE command interface 31/123 4.10 program/erase suspend command the program/erase suspend command pauses a program or block erase operation. the command can be addressed to any bank and is required to restart a suspended operation. one bus write cycle is required to issue the program/erase suspend command. once the program/erase controller has paused, bits sr7, sr6 and/ or sr2 of the status register are set to ?1?. the following commands are accepted during program/erase suspend: ? program/erase resume ? read array (data from erase-suspended block or program-suspended word is not valid) ? read status register ? read electronic signature ? read cfi query ? read efa ? clear status register additionally, if the suspended operation is a block erase then the following commands are also accepted: ? set configuration register ? program (except in erase-suspended block) ? buffer program (except in erase-suspended blocks) ? block lock ? block lock-down ? block unlock ?program efa during an erase suspend the block being erased can be protected by issuing the block lock or block lock-down commands. when the program/erase resume command is issued the operation completes. it is possible to accumulate multiple suspend operations. for example, it is possible to suspend an erase operation, start a program operation, suspend the program operation, and then read the array. if a program command is issued during a block erase suspend, the erase operation cannot be resumed until the program operation has completed. the program/erase suspend command does not change the read mode of the banks. if the suspended bank was in read efa, read status register, read electronic signature or read cfi query mode, the bank remains in that mode and outputs the corresponding data. refer to chapter 11 for detailed information about simultaneous operations allowed during program/erase suspend. during a program/erase suspend, the device can be placed in standby mode by taking chip enable to v ih . program/erase is aborted if reset, rp , goes to v il . see appendix c , figure 26: program suspend and resume flowchart and pseudocode for flowcharts for using the program/erase suspend command.
command interface m58pr512le, M58PR001LE 32/123 4.11 program/erase resume command the program/erase resume command restarts the program or erase operation suspended by the program/erase suspend command. one bus write cycle is required to issue the command. the command can be issued to any address. the program/erase resume command does not change the read mode of the banks. if the suspended bank was in read status register, read electronic signature or read cfi query mode, the bank remains in that mode and outputs the corresponding data. if a program command is issued during a block erase suspend, then the erase cannot be resumed until the program operation is complete. see appendix c , figure 26: program suspend and resume flowchart and pseudocode and figure 28: erase suspend and resume flowchart and pseudocode for flowcharts for using the program/erase resume command. 4.12 protection register program command the protection register program command programs the user otp area of the protection register and the two protection register locks. the device features 16 otp areas of 128 bits and one otp area of 64 bits, as shown in figure 6: protection register memory map . the areas are programmed one word at a time. when shipped, all bits in the area are set to ?1?. only the user can program the bits to ?0?. two bus write cycles are required to issue the protection register program command. the first bus cycle sets up the pr otection register program command. the second latches the address and data to be programmed to the protection register and starts the program/erase controller. read operations to the bank being programmed output the status register content after the program operation has started. attempting to program a previously-protected protection register results in a status register error. the protection register program cannot be suspended. dual operations between the efa and the protection register memory space are not allowed (see table 20: dual operation limitations for details). the two protection register locks are used to protect the otp areas from further modification. the protection of the otp areas is not reversible. refer to figure 6: protection register memory map for details on the lock bits. see appendix c , figure 31: protection register program flowchart and pseudocode for a flowchart for using the protection register program command.
m58pr512le, M58PR001LE command interface 33/123 4.13 set configuration register command the set configuration register command writes a new value to the configuration register. two bus write cycles are required to issue the set configuration register command. the first cycle sets up the set configuration register command and the address corresponding to the configuration register content. the second cycle writes the configuration register data and the confirm command. the configuration register data must be written as an address during the bus write cycles, such as a0 = cr0, a1 = cr1, ?, a15 = cr15. addresses a16-amax are ignored. read operations output the array content after the set configuration register command is issued. the read electronic signature command is required to read the updated contents of the configuration register. 4.14 block lock command the block lock command is used to lock a block and prevent program or erase operations from changing the data in it. all blocks are locked after power-up or reset. two bus write cycles are required to issue the block lock command. the first bus cycle sets up the block lock command. the second bus write cycle latches the block address and locks the block. the lock status can be monitored for each block using the read electronic signature command. ta b l e 2 1 shows the lock status after issuing a block lock command. once set, the block lock bits remain set even after a hardware reset or power-down/power- up. they are cleared by a block unlock command. refer to section 12: block locking for a detailed explanation. see appendix c , figure 29: main array and efa locking operations flowchart and pseudocode for a flowchart for using the lock command. 4.15 block unlock command the block unlock command unlocks a block, allowing the block to be programmed or erased. two bus write cycles are required to issue the block unlock command. the first bus cycle sets up the block unlock command. the second bus write cycle latches the block address and unlocks the block. the lock status can be monitored for each block using the read electronic signature command. ta b l e 2 1 shows the protection status after issuing a block unlock command. refer to section 12: block locking for a detailed explanation and appendix c , figure 29: main array and efa locking operations flowchart and pseudocode for a flowchart for using the block unlock command.
command interface m58pr512le, M58PR001LE 34/123 4.16 block lock-down command the block lock-down command locks down a locked or unlocked block. a locked-down block cannot be programmed or erased. the lock status of a locked-down block cannot be changed when wp is low, v il . when wp is high, v ih, the lock-down function is disabled and the locked blocks can be individually unlocked by the block unlock command. two bus write cycles are required to issue the block lock-down command. the first bus cycle sets up the block lock-down command. the second bus write cycle latches the block address and locks-down the block. the lock status can be monitored for each block using the read electronic signature command. locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. ta bl e 2 1 shows the lock status after issuing a block lock-down command. refer to section 12: block locking for a detailed explanation and appendix c , figure 29: main array and efa locking operations flowchart and pseudocode for a flowchart for using the lock-down command. 4.17 blank check command the blank check command checks whether a main array block has been completely erased. only one block at a time can be checked. two bus cycles are required to issue the blank check command: the first bus cycle writes the blank check co mmand to any address in the block to be checked. the second bus cycle writes the blank check confirm command (d0h) to any address in the block to be checked and starts the blank check operation. if the second bus cycle is not blank check confirm, status register bits sr4 and sr5 are set to ?1? and the command aborts. once the command is issued the addressed bank automatically enters the status register mode and further reads within the bank output the status register contents. the only operation permitted during blank check is read status register. dual operations are not supported while a blank check operation is in progress. blank check operations cannot be suspended and are not allowed while the device is in program/erase suspend. the sr7 status register bit indicates the status of the blank check operation in progress: sr7 = ?0? means that the blank check operatio n is still ongoing. sr7 = ?1? means that the operation is complete. the sr5 status register bit goes high (sr5 = ?1?) to indicate that a blank check operation has failed. at the end of the operation the bank remains in the read status register mode until another command is written to the command interface. see appendix c , figure 30: blank check flowchart and pseudocode for a suggested flowchart for using the blank check command. typical blank check times are provided in table 22: program/erase times and endurance cycles .
m58pr512le, M58PR001LE command interface 35/123 4.18 set enhanced configur ation register command the set enhanced configuration register command is used to write a new value to the enhanced configuration register. two bus write cycles are required to issue the set enhanced configuration register command. the first cycle sets up the set enhanced configuration register command and the address corresponding to the enhanced configuration register contents. the second cycle writes the enhanced configuration register data and the confirm command. the enhanced configuration register data must be written as an address during the bus write cycle, such as a0 = ecr0, a1 = ecr1, ?, a15 = ecr15. if the set enhanced configuration register setup write cycle is not followed by the set enhanced configuration register confirm command (04h), status register bits sr4 and sr5 are set. after successfully executing this command, the bank addressed returns to read array state. 4.19 read efa block command the read efa block command places the addressed bank in the read efa mode, where all addresses in the addressed bank are remapped to efa block addresses. when the device is in read efa mode, the main array blocks in the addressed bank can no longer be accessed until a read array command is issued to the bank. one bus write cycle is required to issue the read efa block command. once a bank is in read efa mode, subsequent read operations from any address within the efa block output the efa data from the efa block. see table 4: efa memory map for details. efa blocks can be read through asynchronous or single synchronous read operations only. the asynchronous page read mode cannot be used to read the efa blocks. if a read efa command is issued in a bank that is programming or erasing, the read mode of the bank changes to read efa mode.
command interface m58pr512le, M58PR001LE 36/123 4.20 program efa block command the program efa block command programs a single word to an efa block. two bus write cycles are required to issue the program efa block command. the first bus cycle sets up the program efa block command. the second cycle latches the address and data to be programmed and starts the program/erase controller. once the programming has started, read operations in the bank being programmed output the status register contents. issuing the program efa block command to an address outside the efa block address range generates a program error in the status register (sr4=1). a read efa block command is required to return the bank to read efa mode. refer to section 11 for detailed information about simultaneous operations allowed in the banks not being programmed. typical efa program times are given in table 22: program/erase times and endurance cycles . the program operation aborts if reset, rp , is at v il . as data integrity cannot be guaranteed when a program efa block operation is aborted, the word must be reprogrammed. see appendix c , figure 24: program and efa block program flowchart and pseudocode for the flowchart for using the program efa block command. 4.21 erase efa block command the erase efa block command erases an efa block. it sets all the bits within the selected block to '1', and all previous data in the block is lost. if the efa block is protected, then the erase operation aborts, the data in the efa block is not changed, and the status register outputs the error. two bus write cycles are required to issue the command. the first bus cycle sets up the erase efa block command. the second latches the efa block address and starts the program/erase controller. the first cycle brings the efa plane to the foreground and latches the address of the efa block to be erased. reading from the bank when the efa plane is in the foreground returns the status register. once the erase operation has started, read operations in the bank being erased output the status register contents. if the erase efa block confirm command code is not issued in the second bus cycle, status register bits sr4 and sr5 are set, the command is aborted, and the addressed bank remains in the read status register mode. issuing the erase efa block command outside the efa block address range generates an error in the status register (sr5=1). the erase efa block operation aborts if reset, rp , is at v il . as data integrity cannot be guaranteed when the erase efa block operation is aborted, the block must be erased again. refer to section 11: dual operations and multiple bank architecture section for detailed information about simultaneous operations allowed with array and non-array blocks. typical erase times are provided in table 22: program/erase times and endurance cycles . see appendix c , figure 27: block erase and efa bloc k erase flowchart and pseudocode for a suggested flowchart for using the erase efa block command.
m58pr512le, M58PR001LE command interface 37/123 4.22 suspend efa block command the suspend efa block command pauses a program or erase efa block operation. the command can be addressed to any bank. the resume efa block command is required to restart the suspended operation. one bus write cycle is required to issue the suspend efa block command. once the program/erase controller has paused, bits sr7, sr6 and/ or sr2 of the status register are set to '1'. the following commands are accepted during suspend efa block: ? resume efa block ? read array ? read efa block (data from erase-suspended blocks or program-suspended words is not valid) ? read status register ? read electronic signature ? read cfi query. ? clear status register additionally, if the suspended operation was an erase efa block operation then the following commands are also accepted: ? set configuration register ? program efa block (except in the erase-suspended block) ? program and buffer program in the main array ? block lock ? block lock-down ? block unlock ? efa block lock ? efa block lock-down ? efa block unlock during suspend efa block the efa block being erased can be protected by issuing the efa block lock or efa block lock-down commands. when the resume efa block command is issued, the operation is resumed and completes. the suspend efa block operation can be repeated. for example, it is possible to suspend an erase efa block operation, to start a program efa block operation, to suspend the program operation, and then read efa locations. if a program efa block command is issued during a suspend efa block operation, the erase efa block operation cannot be resumed until the program operation has completed. the state of the bank where the command was issued do not change. refer to section 11 for detailed information about simultaneous operations allowed during a suspend efa block operation.
command interface m58pr512le, M58PR001LE 38/123 during a suspend efa block operation, the device can be placed in standby mode by taking chip enable to v ih . program/erase is aborted if reset, rp , is v il . see appendix c , figure 26: program suspend and resume flowchart and pseudocode and figure 28: erase suspend and resume flowchart and pseudocode for flowcharts for using the suspend efa block command. 4.23 resume efa block command the resume efa block command restarts the program or erase efa block operation suspended by the suspend efa block command. one bus write cycle is required to issue the command. the command can be issued to any address. the resume efa block command does not change the read mode of the banks. if a program efa block command is issued while an erase efa block operation has been suspended, then the erase operation cannot be resumed until the program operation has completed. see appendix c , figure 26: program suspend and resume flowchart and pseudocode and figure 28: erase suspend and resume flowchart and pseudocode for flowcharts for using the resume efa block command. 4.24 lock efa block command the lock efa block command is used to lock an efa block and prevent program or erase operations from changing the data in it. all efa blocks are locked after power-up or reset. two bus write cycles are required to issue the lock efa block command. the first bus cycle sets up the lock efa block command. the second bus cycle latches the block address and locks the block. the lock status can be monitored for each efa block using the read electronic signature command . once set, the block lock bits remain set even after a hardware reset or a power-down/ power-up sequence. they are cleared by an unlock efa block command. program or erase operations to a locked efa block generates an error in the status register (sr1=1). refer to section 12: block locking for a detailed explanation. see appendix c , figure 29: main array and efa locking operations flowchart and pseudocode for a flowchart for using the lock efa block command.
m58pr512le, M58PR001LE command interface 39/123 4.25 unlock efa block command the unlock efa block command unlocks an efa block, allowing the efa block to be programmed or erased. two bus write cycles are required to issue the unlock efa block command. the first bus cycle sets up the unlock efa block command. the second bus write cycle latches the block address and unlocks the block. the lock status can be monitored for each efa block using the read electronic signature command . refer to section 12: block locking for a detailed explanation and to appendix c , figure 29: main array and efa locking operations flowchart and pseudocode for a flowchart for using the unlock efa block command. 4.26 lock-down efa block command the lock-down efa block command locks down a locked or unlocked efa block. a locked-down efa block cannot be programmed or erased. the lock status of a locked- down efa block cannot be changed when wp is low, v il . when wp is high, v ih , the lock- down function is disabled and the locked efa blocks can be individually unlocked by issuing the unlock efa block command. two bus write cycles are required to issue the lock-down efa block command. the first bus cycle sets up the lock-down efa block command. the second bus write cycle latches the block address and locks down the block. the lock status can be monitored for each efa block using the read electronic signature command . locked-down efa blocks revert to the locked (and not locked-down) state when the device is reset on power-down. ta bl e 2 1 shows the lock status after issuing a lock-down efa block command. refer to section 12: block locking for a detailed explanation and to appendix c , figure 29: main array and efa locking operations flowchart and pseudocode for a flowchart for using the lock-down efa block command.
command interface m58pr512le, M58PR001LE 40/123 table 7. standard commands commands cycles bus operations (1) 1st cycle 2nd cycle op. add data op. add data read array 1+ write bka ffh read wa rd read status register 1+ write bka 70h read bka (2) srd read electronic signature 1+ write bka 90h read bka (2) esd read cfi query 1+ write bka 98h read bka (2) qd clear status register 1 write x 50h block erase 2 write bka or ba (3) 20h write ba d0h program 2 write bka or wa (3) 41h write wa pd buffer program n+4 (4) write ba e9h write ba n write pa 1 pd 1 write pa 2 pd 2 write pa n+1 pd n+1 write x d0h program/erase suspend 1 write x b0h program/erase resume 1 write x d0h protection register program 2 write pra c0h write pra prd set configuration register 2 write crd 60h write crd 03h block lock 2 write bka or ba (3) 60h write ba 01h set enhanced configuration register 2 write ecrd 60h write ecrd 04h block unlock 2 write bka or ba (3) 60h write ba d0h block lock-down 2 write bka or ba (3) 60h write ba 2fh blank check 2 write ba bch write ba d0h read efa block 1+ write bka 94h read wa rd program efa block 2 write bka or wa (3) 44h write wa pd erase efa block 2 write bka or ba (3) 24h write ba d0h suspend efa block 1 write x b0h resume efa block 1 write x d0h lock efa block 2 write bka or ba (3) 64h write ba 01h unlock efa block 2 write bka or ba (3) 64h write ba d0h lock-down efa block 2 write ba 64h write ba 2fh 1. x = don't care, wa = word address in targeted bank, rd = read data, srd = status regi ster data, esd = electronic signature data, qd = query data, ba = block address, bka = bank address, pa = program address, pd = program data, pra = protection register address, prd = protection register data, crd = configuration register data, ecrd = enhanced configuration register data. 2. must be same bank as in the first cy cle. the signature addresses are listed in table 9 . 3. any address within the bank can be used. 4. n+1 is the number of words to be programmed.
m58pr512le, M58PR001LE command interface 41/123 table 8. factory program command (1) command phase cycles bus write operations 1st 2nd 3rd final -1 final add data add data add data add data add data buffer enhanced factory program setup 2 bka or wa (2) 80h wa 1 d0h program/ verify (3) 512 wa 1 pd 1 wa 1 pd 2 wa 1 pd 3 wa 1 pd 511 wa 1 pd 512 exit 1 not ba 1 (4) ffffh 1. wa = word address in targeted bank, bka = bank address, pd = program data, ba = block address, x = don?t care. 2. any address within the bank can be used. 3. the program/verify phase can be executed any number of times as long as the da ta is programmed to the same block. 4. wa 1 is the start address, not ba 1 = not block address of wa 1 . table 9. electronic signature codes code address (h) data (h) manufacturer code bank address + 00 0020 device code 512 mbit bank address + 01 8819 1 gbit 880f block protection main block locked block address + 02 dq1, dq0 = 01 unlocked dq1, dq0 = 00 locked and locked-down dq1, dq0 = 11 unlocked and locked-down dq1, dq0 = 10 efa block locked dq5, dq4 = 01 unlocked dq5, dq4 = 00 locked and locked-down dq5, dq4 = 11 unlocked and locked-down dq5, dq4 = 10 configuration register bank address + 05 cr (1) enhanced configuration register bank address + 06 ecr (1) protection register pr0 lock st factory default bank address + 80 0002 otp area permanently locked 0000 protection register pr0 bank address + 81 unique device number bank address + 84 bank address + 85 otp area bank address + 88 protection register pr1 through pr16 lock bank address + 89 prld (1) protection registers pr1-pr16 bank address + 8a otp area bank address + 109 1. cr = configuration regist er, ecr = enhanced configurati on register, prld = protection register lock data.
command interface m58pr512le, M58PR001LE 42/123 figure 6. protection register memory map table 10. protection register locks lock description number address bits lock 1 80h bit 0 preprogrammed to protect unique device number, address 81h to 84h in pr0 bit 1 protects 64 bits of otp area, address 85h to 88h in pr0 bits 2 to 15 reserved lock 2 89h bit 0 protects 128 bits of otp area pr1 bit 1 protects 128 bits of otp area pr2 bit 2 protects 128 bits of otp area pr3 ---- ---- bit 13 protects 128 bits of otp area pr14 bit 14 protects 128 bits of otp area pr15 bit 15 protects 128 bits of otp area pr16 ai07563 user programmable otp unique device number protection register lock 1 0 88h 88h 85h 84h 81h 80h user programmable otp protection registers user programmable otp 10 432 975 13 12 10 11 8 6 14 15 pr1 pr16 pr0 89h 8ah 91h 102h 109h
m58pr512le, M58PR001LE program operations 43/123 5 program operations the m58pr512le and M58PR001LE have inno vative features specially developed to improve the storage flexibility and effi ciency of nor flash memory arrays. data and code can be stored more efficiently by using the right combination of program methods and program modes. there are two types of program methods that use commands that consist of one or more sequential bus write operations interpreted by the command interface: single word program method, which uses the program command. buffered program method, which uses either the buffer program command or the buffer enhanced factory program command. there are two program modes: control program mode object program mode. the control program mode supports the two program methods, whereas the object program mode only supports the buffered program method. this new logical organization of program operations is made possible by the device architecture, and, in particular, by the new concept of program regions. 5.1 program regions each flash memory block is divided into 256 program regions (see figure 7: program regions configured in control or object program mode ). erase operations have a block granularity, whereas program operations have a program region granularity. the user can configure each program region to be programmed either in the control program mode or in the object program mode. a given block can contain program regions configured in the control program mode and others configured in the object program mode. special care should be taken when selecting the programming mode for the program regions because once the program regions are configured, their program mode cannot be changed until the entire block is erased. each program region is split into 32 segments of 32 bytes and each segment is subdivided into two halves, ?a? and ?b?. address bit a3 determines whether a bit belongs to the ?a? half (a3 = 0) or to the ?b? half (a3 = 1).
program operations m58pr512le, M58PR001LE 44/123 5.2 program modes there are two program modes, which allow the flash memory to store different types of data: control program mode and object program mode. 5.2.1 control program mode the control program mode is best suited to the storage of small, dynamic information. typically such data is contained within one pr ogram region and it is frequently updated and/or new data is added to it. program regions are configured in the control program mode by programming data only to the ?a? halves (bit a3= 0) of the segments they contain. the ?b? halves of the segments must remain erased, meaning that they should not contain any zeros (see figure 7: program regions configured in control or object program mode ). in a program region of 1 kbyte configured in the control program mode, only 512 bytes of data can be stored. when the program regions are configured in the control program mode, any program method can be used: the single word or the buffered program methods. once a program region has been configured in the control program mode, if a zero is written to a ?b? half of one of its segments, the program operation is terminated and an error is generated. the status register bits sr4 and sr9 are set to ?1?. (refer to status register and to table 12: relationships between program methods and program modes for details.) the program mode of a program region configured in the control program mode can only be changed by first erasing the block that contains the program region. 5.2.2 object program mode the object program mode is best suited to the storage of large amounts of static information. in a program region of 1 kbyte configured in the object program mode, 1 kbyte of data can be stored. when a program region is configured in the object program mode, it cannot be re- programmed or have new data added without first erasing the entire block that contains the program region. program regions are configured in the object program mode simply by programming at least one bit in the ?b? half (a3 = 1) of one of the segments they contain. if the programmed data is smaller than 1 kbyte, the unused space remains in the erased state (all the bits set to ffffh), but can no longer be used to program data. see figure 7: program regions configured in control or object program mode . when the program regions are configured in the object program mode, only the buffered program methods can be used. if an attemp t is made to use the single word program method, the program operation is aborted and status register error bits sr4 and sr8 are set to ?1?. (refer to status register and to table 12: relationships between program methods and program modes , for details.)
m58pr512le, M58PR001LE program operations 45/123 figure 7. program regions configured in control or object program mode 5.3 program methods the device supports two types of program methods: single word program method, which is used to program a single word to a specific address of the memory array. buffered program methods, which can be split into two different methods: ? buffer program method, which uses the device's write buffer to speed up programming. the data is written into the write buffer and then programmed to the specified block address. ? buffer enhanced factory program method, which is developed to speed up programming in manufacturing environments where the programming time is critical. the data is written in the write buffer and then programmed to the specified block. the following sections describe the relationship between program commands and program methods in detail. see table 12: relationships between program methods and program modes and table 11: program methods available with each program mode . program region 0 1 kbyte (512 byte programmable) 128 kword block data 2 data 4 f f f f f f f f segment 30 data (n ? 4) data (n ? 2) data n segment 3 segment 2 segment 1 segment 0 ... program region in control program mode f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f a halves (a3 = 0) b halves (a3 = 1) ... object 1 kbyte ai10135 segment 31 : : : : : program region 1 1 kbyte (512 byte programmable) program region 254 1 kbyte (512 byte programmable) program region 255 1 kbyte (512 byte programmable) data 1 data 3 data (n ? 3) data (n ? 1) segment 30 segment 3 segment 2 segment 1 segment 0 segment 31 f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f program region in object program mode
program operations m58pr512le, M58PR001LE 46/123 5.3.1 single word program method the single word program method is based on the program command. it is only supported by program regions configured in the control program mode. if the single word program method is attempted in a program region configured in the object program mode, the program operation is aborted and status register bits sr4 and sr8 are set. see section 4: command interface for a detailed description of the program command. in program regions configured in the control program mode, the program command can be issued several times. using the single word program method to program one or more bits to '0' in the ?b? halves of the segments (a3 = 1) of an erased or already programmed program region generates an error: in the case of an erased program region, this is considered an illegal operation that sets status register bits sr4 and sr9. in the case of an already programmed program region, an error is always generated because: ? to be able to write to a program region configured in the object program mode, the entire block that contains the program region must be erased first. ? it is not allowed to write to the ?b? halves of the segments of a program region configured in the control program mode. 5.3.2 buffer program method the buffer program method is based on the buffer program command and uses a 1 kbyte write buffer to speed up programming. the data is written to the write buffer and then programmed to the specified main array location. the buffer program method is supported regardless of the program mode of the program regions. when using the buffer program method in a program region configured in the object program mode, the start address must be aligned to the 1 kbyte write buffer. when using the buffer program method in a program region configured in the control program mode, the address to be programmed must be located inside the ?a? halves of the program region?s segments (addresses with a3 = 0) and the ?b? halves of the segments (addresses with a3= 1) must be filled only with ffffh data. the buffer program command can be issued several times to program regions configured in the control program mode. the buffer program command can only be issued once in program regions configured in the object program mode. attempts to program the same program regions by re-issuing the buffer program command leads to data corruption. see section 4: command interface for a detailed description of the buffer program command.
m58pr512le, M58PR001LE program operations 47/123 5.3.3 buffer enhanced factory program method the buffer enhanced factory program method is based on the buffer enhanced factory program command. the buffer enhanced factory program method is supported by the program regions, regardless of the program mode in which they are configured. in this program method, the pr ogram region (1 kbyte) must be completely f illed, regardless of the program mode used. if the size of the data to be written is less than 1 kbyte, the remaining addresses in the program region must be filled with ffffh. when using the buffer enhanced factory program method in a program region configured in the control program mode, the addresses to be programmed must be located in the ?a? half of the program regions? segments (a3 = 0) and the ?b? half of the segments (a3 = 1) must be filled only with ffffh. see section 4: command interface for a detailed description of the buffer enhanced factory program command. table 11. program methods available with each program mode program mode program methods (1) 1. x means available. single word program buffered program buffer program buffer enhanced factory program control program mode x x x object program mode x x table 12. relationships between program methods and program modes program region status address bit a3 value program method buffered program single word program buffer program buffer enhanced factory program erased a3 = 0 (?a? half) program region configured in control program mode program region configured in control program mode a3 = 1 (?b? half) program region configured in object program mode not allowed. program aborted, status register error bits sr4 and sr9 set control program mode a3 = 0 (?a? half) program operation successful a3 = 1 (?b? half) not allowed. program aborted, stat us register error bits sr4 and sr9 set object program mode a3 = 0 (?a? half) subsequent program not allowed. program aborted, stat us register error bits sr4 and sr8 set a3 = 1 (?b? half)
status register m58pr512le, M58PR001LE 48/123 6 status register the status register provides information on the current or previous program or erase operations. issue a read status register command to read the contents of the status register (refer to section 4.2 for more details on the command itself). to output the contents, the status register is latched and updated on the falling edge of the chip enable or output enable signals, and can be read until chip enable or output enable returns to v ih . the status register can only be read using single asynchronous or single synchronous reads. bus read operations from any address within the bank always read the status register during program and erase operations if no read array command has been issued. the various bits convey information about the status and any errors of the operation. bits sr7, sr6, sr2 and sr0 give information on the status of the device and are set and reset by the device. bits sr9, sr8, sr5, sr4, sr3 and sr1 give information on errors. they are set by the device but must be reset by issuing a clear status register command or a hardware reset. if an error bit is set to ?1? the status register should be reset before issuing another command. the bits in the status register are summarized in table 13: status register bits . refer to ta bl e 1 3 in conjunction with the following text descriptions. 6.1 control program mode status bit (sr9) the control program mode status bit, sr9, indicates whether an error occurred while writing to a program region that is configured in control program mode. the sr9 bit should be read once the program/erase controller status bit sr7 is set to ?1? (program/erase controller inactive). sr9 is set to 1 when the user attempts to program object data in a control mode region. when: sr9 = 0, the program operation completed successfully. sr9 = 1, the program operation failed. once set to ?1?, sr9 can only be cleared by issuing a clear status register command or through a hardware reset. sr9 should be cleared before a new program command is issued, otherwise the new command appears to fail.
m58pr512le, M58PR001LE status register 49/123 6.2 object program mo de status bit (sr8) the object program mode status bit, sr8, indicates whether an error occurred while writing to a program region that was configured in the object program mode. the sr8 bit should be read once the program/erase controller status bit sr7 is set to ?1? (program/erase controller inactive). sr8 is set to 1 when the user attempts to rewrite an object mode region. when: sr8 = 0, the program operation completed successfully. sr8 = 1, the program operation failed. once set, sr8 can only be cleared by issuing a clear status register command or through a hardware reset. sr8 should be cleared before a new program command is issued, otherwise the new command appears to fail. 6.3 program/erase controller status bit (sr7) the program/erase controller status bit indicates whether the program/erase controller is active or inactive in any bank. when: sr7 = 0, the program/erase controller is active. sr7 = 1, the program/erase controller is inactive, and the device is ready to process a new command. the program/erase controller status bit is set to ?0? immediately after a program/erase suspend command is issued until the program/erase controller pauses. after the program/erase controller pauses, the bit is set to ?1?. 6.4 erase suspend status bit (sr6) the erase suspend status bit indicates that an erase operation has been suspended in the addressed block. when: sr6 = 0, no program/erase suspend command has been issued. sr6 = 1, a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. the erase suspend status bit should only be considered valid when the program/erase controller status bit is set to ?1? (program/erase controller inac tive). sr6 is set within the erase suspend latency time of the program/erase suspend command being issued, therefore, the memory may still complete the operation rather than entering suspend mode. when a program/erase resume command is issued, the erase suspend status bit is reset to ?0?.
status register m58pr512le, M58PR001LE 50/123 6.5 erase status bit (sr5) the erase status bit identifies if there is an error during a block erase operation. when: sr5 = 0, no error occurred. sr5 = 1, the program/erase controller applied the maximum number of pulses to the block or bank and still failed to verify that it has erased correctly. the erase status bit should be read once the program/erase controller status bit is set to ?1? (program/erase controller inactive). once set, the erase status bit must be cleared by a clear status register command or a hardware reset. this must be done before a new erase command is issued, otherwise the new command appears to fail. 6.6 program status bit (sr4) the program status bit identifies if there is an error during a program operation. the program status bit should be read once the program/erase controller status bit is set to ?1? (program/erase controller inactive). when: sr4 = 0, no error occurred. sr4 = 1, the program/erase controller applied the maximum number of pulses to the word and still failed to verify that it programmed correctly. attempting to program a '1' to an already programmed bit while v pp = v pph also sets the program status bit to ?1?. if v pp is different from v pph , sr4 remains set to '0' and the attempt is not shown. once set to '1', the program status bit must be cleared by a clear status register command or a hardware reset. this must be done before a new program command is issued, otherwise the new command appears to fail. 6.7 v pp status bit (sr3) the v pp status bit identifies an invalid voltage on the v pp pin during program and erase operations. the v pp pin is only sampled at the beginning of a program or erase operation. program and erase operations are not guaranteed if v pp becomes invalid during an operation. when: sr3 = 0, the voltage on the v pp pin is sampled at a valid voltage. sr3 = 1, the v pp pin has a voltage that is below the v pp lockout voltage, v pplk , the memory is protected, and program and erase operations cannot be performed. once set to ?1?, the v pp status bit must be cleared by a clear status register command or a hardware reset. this must be done before a new program or erase command is issued, otherwise the new command appears to fail.
m58pr512le, M58PR001LE status register 51/123 6.8 program suspend status bit (sr2) the program suspend status bit indicates that a program operation has been suspended in the addressed block. the program suspend status bit is onlyconsidered valid when the program/erase controller status bit is set to ?1? (program/erase controller inactive). when: sr2 = 0, no program/erase suspend command has been issued. sr2 = 1, a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. sr2 is set within the program suspend latency time of the program/erase suspend command being issued, therefor e, the memory may still comple te the operation rather than entering suspend mode. when a program/erase resume command is issued, the program suspend status bit is reset to ?0?. 6.9 block protection status bit (sr1) the block protection status bit dentifies if a program or block erase operation has tried to modify the contents of a locked block. when: sr1 = 0, no program or erase operation has been attempted on a locked block. sr1 = 1, a program or erase operation has been attempted on a locked block. once set to ?1?, the block protection status bit must be cleared by a clear status register command or a hardware reset. this must be done before a new program or erase command is issued, otherwise the new command appears to fail. 6.10 bank write/multiple word program status bit (sr0) the bank write status bit indicates if the addressed bank is programming or erasing. the bank write status bit is only considered valid when the program/erase controller status bit sr7 is set to ?0?. when: sr0 = 0 and sr7 = 0, the addressed bank is executing a program or erase operation. sr0 = 1 and sr7 = 0, a program or erase operation is being executed in a bank other than the one being addressed. during buffer enhanced factory program operations the multiple word program bit, sr0, shows if the device is ready to accept a new word to be programmed to the memory array. when: sr0 = 0, the device is ready for the next word. sr0 = 1, the device is not ready for the next word. for further details on how to use the status register, see the flowcharts and pseudocodes provided in appendix c .
status register m58pr512le, M58PR001LE 52/123 table 13. status register bits bit name type logic level (1) 1. logic level '1' is high, '0' is low. definition sr15- sr10 reserved (2) 2. reserved bits should always be reset to ?0?. sr9 control program mode status error 1 program error in program region configured in control program mode 0 program successful sr8 object program mode status error 1 program error in program region configured in object program mode 0 program successful sr7 p/ec status status 1 ready 0busy sr6 erase suspend status status 1 erase suspended 0 erase in progress or completed sr5 erase status error 1 erase error 0 erase success sr4 program status error 1 program error 0 program success sr3 v pp status error 1v pp invalid, abort 0v pp ok sr2 program suspend status status 1 program suspended 0 program in progress or completed sr1 block protection status error 1 program/erase on protected block, abort 0 no operation to protected blocks sr0 bank write status status 1 sr7 = ?1? not allowed sr7 = ?0? program or erase operation in a bank other than the addressed bank 0 sr7 = ?1? no program or erase operation in the device sr7 = ?0? program or erase operation in addressed bank multiple word program status (buffer enhanced factory program mode) status 1 sr7 = ?1? not allowed sr7 = ?0? the device is not ready for the next word or is going to exit befp mode 0 sr7 = ?1? the device is exiting from befp sr7 = ?0? the device is ready for the next word
m58pr512le, M58PR001LE configuration register 53/123 7 configuration register the configuration register configures the type of bus access that the memory performs. refer to section 10: read modes for details on read operations. the configuration register is set through the command interface using the set configuration register command. the configuration register is volatile: after a reset or a power- down/power-up sequence, the register is set for asynchronous read (cr15=1) and all bits return to their default value. the configuration register bits are described in ta bl e 1 5 . they specify the selection of the burst length, burst x latency and the read operation. refer to figure 8 and figure 9 for examples of synchronous burst configurations. 7.1 read select bit (cr15) the read select bit, cr15, switches between asynchronous and synchronous read operations. when: cr15 = 0: ? read operations in the main array are performed in synchronous burst mode, ? operations to read the status register, electronic signature, cfi and efa are performed in single synchronous mode (see section 10.3: single synchronous read mode for details). cr15 = 1: ? read operations in the main array are performed in asynchronous page mode, ? operations to read the status register, electronic signature, cfi and efa are performed in asynchronous random access mode. synchronous burst read can be performed across banks. on reset or power-up the read select bit is set to ?1? for asynchronous access. 7.2 x latency bits (cr14-cr11) the x latency bits are used during synchronous read operations to set the number of clock cycles between the address being latched and the first data becoming available. for correct operation the x latency bits can only assume the values in table 15: configuration register . ta bl e 1 4 shows how to set the x latency parameter, taking into account the frequency used to read the flash memory in synchronous mode. refer to figure 8: x latency and data output configuration example for an example waveform.
configuration register m58pr512le, M58PR001LE 54/123 7.3 wait polarity bit (cr10) the wait polarity bit sets the polarity of the wait signal used in synchronous burst read mode. when: cr10 = 0, the wait signal is active low. cr10 = 1, the wait signal is active high. during synchronous burst read mode the wait signal indicates whether the data output is valid or a wait state must be inserted. 7.4 wait configuration bit (cr8) the wait configuration bit is used to control the timing of the wait output pin, wait, in synchronous burst read mode. when: cr8 = 0, the wait output pin is asserted during the wait state. cr8 = 1, the wait output pin is asserted one data cycle before the wait state. when wait is asserted, data is not valid and when wait is de-asserted, data is valid. 7.5 burst length bits (cr2-cr0) the burst length bits set the number of words to be output during a synchronous burst read operation as result of a single address latch cycle. they can be set for 8 words, 16 words, or continuous burst, where all the words are read sequentially. in continuous burst mode the burst sequence can cross bank boundaries. in continuous burst mode, the device asserts the wait signal to indicate that a delay is necessary before the data is output. in continuous burst mode, if the starting address is not aligned to the 16-word boundary, wait is asserted when the burst sequence crosses the first 16-word boundary. this indicates that the device needs an internal delay to read the successive words in the array. table 14. x latency settings f max t kmin x latency 40 mhz 25 ns 4 54 mhz 19 ns 5 66 mhz 15 ns 6 108 mhz 9 ns 10
m58pr512le, M58PR001LE configuration register 55/123 in the worst case scenario, the number of wait states is one clock cycle less than the latency setting. wait is asserted only once during a continuous burst access. see also table 16: burst type definition . cr9, cr7, cr6, cr5, cr4 and cr3 are reserved for future use. table 15. configuration register bit description value description cr15 read select 0 synchronous read 1 asynchronous read (default at power-on) cr14-cr11 x latency 0011 3 clock latency 0100 4 clock latency 0101 5 clock latency 0110 6 clock latency 0111 7 clock latency 1000 8 clock latency 1001 9 clock latency 1010 10 clock latency 1011 11 clock latency 1100 12 clock latency 1101 13 clock latency 1110 14 clock latency 1111 15 clock latency (default) other configurations reserved cr10 wait polarity 0 wait is active low (default) 1 wait is active high cr9 reserved (1) 1. reserved bits should be cleared to ?0?. cr8 wait configuration 0 wait is active during wait state 1 wait is active one data cycl e before wait state (default) 1 cr7-cr3 reserved (1) cr2-cr0 burst length 010 8 words (wrap only) 011 16 words (wrap only) 111 continuous (default, no wrap only)
configuration register m58pr512le, M58PR001LE 56/123 figure 8. x latency and data output configuration example 1. the settings shown are x latency = 4. t qvk_cpu is the data setup time required by the system cpu. table 16. burst type definition start address 8 words 16 words continuous burst 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9- 10-11-12-13-14-15 0-1-2-3-4-5-6... 1 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10 -11-12-13-14-15-0 1 -2-3-4-5-6-7... 2 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10 -11-12-13-14-15-0-1 2-3-4-5-6-7-8... 3 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11 -12-13-14-15-0-1-2 3-4-5-6-7-8-9... ... 7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14 -15-0-1-2-3-4-5-6 7-8-9-10-11-12-13... ... 12 12-13-14-15-8-9-10-11 12-13-14-15-0-1-2 -3-4-5-6-7-8-9-10-11 12-13-14-15-16-17... 13 13-14-15-8-9-10-11-12 13-14-15-0-1-2-3- 4-5-6-7-8-9-10-11-12 13-14-15-16-17-18... 14 14-15-8-9-10-11-12-13 14- 15-0-1-2-3-4-5-6-7-8-9-10- 11-12-13 14-15-16-17-18-19... 15 15-8-9-10-11-12-13-14 15-0-1-2-3-4-5-6- 7-8-9-10-11-12-13-14 15-16-17-18-19-20... ai08904b amax-a0 valid address k l dq15-dq0 valid data x-latency valid data 1st cycle 2nd cycle 3rd cycle 4th cycle e tkhkh tqvk_cpu tkhqv
m58pr512le, M58PR001LE configuration register 57/123 figure 9. wait configuration example ai12859 amax-a0 valid address k l dq15-dq0 valid data wait cr8 = '0' cr10 = '0' wait cr8 = '1' cr10 = '0' valid data not valid valid data e wait cr8 = '0' cr10 = '1' wait cr8 = '1' cr10 = '1'
enhanced configuration register m58pr512le, M58PR001LE 58/123 8 enhanced configuration register the ecr (enhanced configuration register) enables the deep power-down mode and configures the output driver strength. it is set through the command interface using the set enhanced configuration register command. the contents of the ecr can be read by is suing the read electronic signature command, and then by reading from the bank base address + 06h. the ecr is volatile: after a reset or a power-down/power-up sequence the register is set to the default value. the configuration register bits are described in ta b l e 1 7 . 8.1 deep power-down mode bit (ecr15) the deep power-down mode bit, ecr15, enable the deep power-down mode. the device can only enter the deep power-down mode from standby, by, in any order, asserting the dpd pin and setting ecr15 to ?1?. when the device is in the deep power-down mode, de-asserting the dpd pin and/or resetting ecr15 causes the device to revert to standby mode. 8.2 deep power-down polarity bit (ecr14) the deep power-down polarity bit sets the polarity of the dpd signal. when: ecr14 = 0, the dpd signal is active low (default). ecr14 = 1, the dpd signal is active high. 8.3 output driver cont rol bits (ecr2-ecr0) the output driver control bits, ecr0, ecr1, and ecr2 select the output driver impedance best suited to the system requirements. after reset or power-up the output driver control bits are set to the enhanced configuration register default value (ecr2-ecr0 = 100, that is 30 (30 pf) (default)). optimum performance is only achieved if the output driver impedance is properly configured. once a configuration has been selected, all data and wait output drivers are set to the same setting. ta bl e 1 7 lists the output driver impedances at v ddq /2 and the loads that correspond for each ecr2-ecr0 bit configuration.
m58pr512le, M58PR001LE enhanced configuration register 59/123 table 17. enhanced configuration register bit description value description ecr15 deep power-down mode 0 dpd mode disabled (default) 1 dpd mode enabled ecr14 dpd polarity 0 dpd is active low (default) 1 dpd is active high ecr13-ecr3 reserved (1) 1. reserved bits should be cleared to ?0?. ecr2-ecr0 output driver impedance 001 90 (10 pf) 010 60 (15 pf) 011 45 (20 pf) 100 30 (30 pf) (default) 101 20 (35 pf) 110 15 (40 pf) other configurations reserved
extended flash array (efa) m58pr512le, M58PR001LE 60/123 9 extended flash array (efa) in addition to its main array, the m58prxxxle features an efa that is divided into 4 blocks of 4 kwords each. see table 4: efa memory map . the efa blocks are accessed through a separate set of commands (see section 4: command interface for details). the operations available on the efa blocks are asynchronous random access read, single synchronous read, (single word) program, erase, block lock, block unlock, and block lock- down. the efa blocks support program/erase suspend and dual operations with the main array. dual operations between the efa and the otp area are not supported. see table 20: dual operation limitations for details.
m58pr512le, M58PR001LE read modes 61/123 10 read modes read operations can be performed in two different ways depending on the settings in the configuration register. if the clock signal is ?don?t care? for the data output, the read operation is asynchronous. if the data output is synchronized with clock, the read operation is synchronous. the read mode and format of the data output are determined by the configuration register. (see section 7: configuration register for details). all banks support both asynchronous and synchronous read operations. 10.1 asynchronous read mode in asynchronous read operations the clock signal is ?don?t care?. the device outputs the data corresponding to the address latched, such as the memory array, status register, common flash interface or electronic signature, d epending on the command issued. cr15 in the configuration register must be set to ?1? for asynchronous operations. asynchronous read operations can be performed in two different ways, asynchronous random access read and asynchronous page read. only asynchronous page read takes full advantage of the internal page storage, therefore, different timings are applied. in asynchronous read mode a page of data is internally read and stored in a page buffer. the page has a size of 16 words and is addressed by address inputs a0, a1, a2 and a3. during the page access, amax-a4 and l must remain stable. the first read operation within the page has a longer access time (t avqv , random access time); subsequent reads within the same page have much shorter access times (t avqv1 , page access time). if the page changes then the normal, longer timings apply again. read operations to read non-array data (status register, electronic signature, cfi) should be performed in asynchronous single word mode. if the asynchronous page mode is used to read non-array data, only the first output data is valid and all subsequent data is not accurately determined. the asynchronous page read mode is not available in the efa. the device features an automatic standby mode. during asynchronous read operations, after a bus inactivity of 150 ns, the device automatically switches to automatic standby mode. in this state the power consumption is reduced to the standby value and the outputs are still driven. in asynchronous read mode, the wait signal is always de-asserted. see table 28: asynchronous read ac characteristics , figure 12: asynchronous random access read ac waveforms and figure 13: asynchronous page read ac waveforms for details.
read modes m58pr512le, M58PR001LE 62/123 10.2 synchronous burst read mode in synchronous burst read mode the data is output in bursts synchronized with the clock. it is possible to perform burst reads across bank boundaries. synchronous burst read mode c an only be used to read the memory array. for other read operations, such as read status register, read cfi, read electronic signature and read efa, single synchronous read or asynchronous random access read must be used. in synchronous burst read mode, the flow of the data output depends on parameters that are configured in the configuration register. a burst sequence starts at the first clock edge after the falling edge of latch enable or chip enable, whichever occurs last. addresses are internally incremented and data is output on each data cycle after a delay which depends on the x latency bits cr14-cr11 of the configuration register. the number of words to be output during a synchronous burst read operation can be configured as 8 words, 16 words, or continuous (burst length bits cr2-cr0). the wait signal may be asserted to indicate to the system that an output delay will occur. this delay depends on the starting address of the burst sequence and on the burst configuration. wait is asserted during the x latency, the wait state, and at the end of an 8- and 16-word burst. it is only de-asserted when output data is valid. in continuous burst read mode, a wait stat e occurs when crossing the first 16-word boundary if the start address is not 16-word aligned. the wait signal can be configured to be active low or active high by setting cr10 in the configuration register. see table 29: synchronous read ac characteristics and figure 14: synchronous burst read ac waveforms for details. 10.3 single synchronous read mode single synchronous read operations are similar to synchronous burst read operations except that the memory outputs the same data until the burst length requirements are satisfied (according to configuration register bits cr2-cr0). single synchronous read operations are used to read the efa, electronic signature, status register, cfi, block protection status, configuration register status or protection register. when the addressed bank is in read cfi, read status register or read electronic signature mode, the wait signal is asserted during the x latency, the wait state and at the end of a 4-, 8- and 16-word burst. it is only de-asserted when the output data is valid. see table 29: synchronous read ac characteristics and figure 14: synchronous burst read ac waveforms for details.
m58pr512le, M58PR001LE dual operations and multiple bank architecture 63/123 11 dual operations and multiple bank architecture the multiple bank architectu re of the m58prxxxle gives greater flexibility for software developers to split the code and data spaces within the memory array. the dual operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased. the dual operations feature means that while programming or erasing in one bank, read operations are possible in another bank with zero latency (only one bank at a time is allowed to be in program or erase mode). if a read operation is required in a bank, which is programming or erasing, the program or erase operation can be suspended. also, if the suspended operation was erase then a program command can be issued to another block. this means the device can have one block in erase suspend mode, one programming and other banks in read mode. bus read operations are allowed in another bank between setup and confirm cycles of program or erase operations. by using a combination of these features, re ad operations are possible at any moment in the m58prxxxle device. dual operations between the efa and either of the cfi, the otp, or the electronic signature memory space are not allowed. ta bl e 2 0 shows which dual operations are allowed or not between the cfi, the otp, the electronic signature locations and the memory array. ta bl e 1 8 and ta bl e 1 9 show the dual operations possible in other banks and in the same bank. table 18. dual operations allowed in other banks status of bank commands allowed in another bank read array read status register read cfi query read electronic signature read efa program, buffer program block erase program/ erase suspend program/ erase resume i d l e ye s ye s ye s ye s ye s ye s ye s ye s ye s programming yes yes yes yes yes ? ? yes ? erasing yes yes yes yes yes ? ? yes ? program suspended ye s ye s ye s ye s ye s ? ? ? ye s erase suspended ye s ye s ye s ye s ye s ye s ? ? ye s
dual operations and multiple bank architecture m58pr512le, M58PR001LE 64/123 table 19. dual operations allowed in same bank status of bank commands allowed in same bank read array read status register read cfi query read electronic signature read efa program, buffer program block erase program/ erase suspend program/ erase resume i d l e ye s ye s ye s ye s ye s ye s ye s ye s ye s programming ? (1) 1. the read array command is accepted but the data ou tput is not guaranteed until the program or erase has completed. ye s ye s ye s ye s ? ? ye s ? erasing ? (1) ye s ye s ye s ye s ? ? ye s ? program suspended ye s (2) 2. not allowed in the block that is being erased or in the program region that is being programmed. ye s ye s ye s ye s ? ? ? ye s erase suspended ye s (2) ye s ye s ye s ye s ye s (2) ?? yes table 20. dual operation limitations otp, efa or cfi data main array bank comments read program/erase while programming or erasing in a main array bank, the otp, cfi data and efa blocks may be read from any other bank. program read while programming to the otp area, read operations are only allowed in the other main array banks. access to efa data or cfi data is not allowed. program/erase read while programming or erasing an efa block, it is not allowed to read otp or cfi data. read operations to the banks whose addresses are not being used to address the efa, are supported.
m58pr512le, M58PR001LE block locking 65/123 12 block locking the m58prxxxle features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. this locking scheme has three levels of protection. lock/unlock - this first level allows so ftware only control of block locking. lock-down - this second level requires hardware interaction before locking can be changed. v pp v pplk - the third level offers a complete hardware protection against program and erase on all blocks. the protection status of each block can be set to locked, unlocked, and locked-down. ta bl e 2 1 defines all of the possible protection states (wp , dq1, dq0), and appendix c , figure 29 shows a flowchart for the locking operations. 12.1 reading a block?s lock status the lock status of every block can be read in the read electronic signature mode of the device. to enter this mode issue the read electronic signature command. subsequent reads at the address specified in ta bl e 9 output the protection status of that block. the lock status is represented by dq0 and dq1. dq0 indicates the block lock/unlock status and is set by the lock command and cleared by the unlock command. dq0 is automatically set when entering lock-down. dq1 indicates the lock-down status and is set by the lock- down command. dq1 cannot be cleared by software, only by a hardware reset or power- down. the following sections explain the operation of the locking system. 12.2 locked state the default status of all blocks on power-up or after a hardware reset is locked (states (0,0,1) or (1,0,1)). locked blocks are fully protected from program or erase operations. any program or erase operations attempted on a locked block returns an error in the status register. the status of a locked block can be changed to unlocked or locked-down using the appropriate software commands. an unlocked block can be locked by issuing the lock command. 12.3 unlocked state unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)) can be programmed or erased. all unlocked blocks return to the locked state after a hardware reset or when the device is powered- down. the status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. a locked block can be unlocked by issuing the unlock command.
block locking m58pr512le, M58PR001LE 66/123 12.4 lock-down state blocks that are locked-down (state (0,1,x)) are protected from program and erase operations (as for locked blocks) but their pr otection status cannot be changed using software commands alone. a locked or unlocked block can be locked down by issuing the lock-down command. locked-down blocks revert to the locked state when the device is reset or powered-down. the lock-down function is dependent on the write protect, wp , input pin. when wp = 0 (v il ), the blocks in the lock-down state (0,1,x) are protected from program, erase and protection status changes. when wp = 1 (v ih ) the lock-down function is disabled (1,1,x) and locked-down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. when the lock-down function is disabled (wp =1) blocks can be locked (1,1,1) and unlocked (1,1,0) as desired. when wp = 0 blocks that were previously locked-down return to the lock-down state (0,1,x) regardless of any changes that were made while wp = 1. device reset or power-down resets all blocks, including those in lock-down, to the locked state. 12.5 locking operations during erase suspend changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock down a block. this is useful in the case when another block needs to be updated while an erase operation is in progress. to change block locking during an erase operation, first write the erase suspend command, then check the status register until it indicates that the erase operation has been suspended. next, write the desired lock command sequence to a block and the lock status is changed. after completing any desired lock, read, or program operations, resume the erase operation with the erase resume command. if a block is locked or locked-down during an erase suspend of the same block, the locking status bits are changed immediately, but wh en the erase is resumed, the erase operation completes. locking operations cannot be performed during a program suspend.
m58pr512le, M58PR001LE block locking 67/123 table 21. lock status current protection status (1) (wp , dq1, dq0) 1. the lock status is defined by the write protect pin and by dq1 (?1? for a locked-dow n block) and dq0 (?1? for a locked block) as read in the read elec tronic signature command with a1 = v ih and a0 = v il . next protection status (1) (wp , dq1, dq0) current state program/erase allowed after block lock command after block unlock command after block lock-down command after wp transition 1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0 1,0,1 (2) 2. all blocks are locked at power -up, so the default configuration is 001 or 101 according to wp status. no 1,0,1 1,0,0 1,1,1 0,0,1 1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0 0,0,1 (2) no 0,0,1 0,0,0 0,1,1 1,0,1 0,1,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0 (3) 3. a wp transition to v ih on a locked block will restore the pr evious dq0 value, giving a 111 or 110.
program and erase times and endurance cycles m58pr512le, M58PR001LE 68/123 13 program and erase times and endurance cycles the program and erase times and the number of program/ erase cycles per block are shown in ta b l e 2 2 . exact erase times may change depending on the memory array condition. the best scenario is when all the bits in the block are at ?0? (pre-programmed). the worst scenario is when all the bits in the block are at ?1? (not preprogrammed). usually, the system overhead is negligible with respec t to the erase time. in the m58prxxxle the maximum number of program/erase cycles depends on the v pp voltage supply used. table 22. program/erase times and endurance cycles (1) (2) parameter condition min typ typical after 100 kw/e cycles max unit v pp = v dd erase efa block (4 kword) 0.7 2.5 s main array block 128 kword) 0.9 4 s program (3) single cell (4) word program (5) 50 230 s buffer program 250 500 s single word (4) word program (5) 50 230 s buffer program 250 500 s buffer (512 words) (buffer program) 2.15 4.3 ms efa block (4 kword) 0.2 0.94 s main array block (128 kword) (buffer program) 0.55 1.1 s suspend latency program 20 30 s erase 20 30 s program/erase cycles (per block) main array block 100 000 cycles efa block 100 000 blank check main array block 3.2 ms
m58pr512le, M58PR001LE program and erase times and endurance cycles 69/123 v pp = v pph erase efa block (4 kword) 0.7 2.5 s main array block (128 kword) 0.9 4 s program (3) single cell (4) word program (5) 50 230 s single word (4) word program (5) 50 230 s buffer enhanced factory program (4) 4.2 s buffer (512 words) buffer program 2.15 4.3 ms buffer enhanced factory program 2.15 ms main block (128 kwords) buffer program 0.55 1.1 s buffer enhanced factory program 0.55 s efa block (4 kwords) 0.2 0.94 s program/erase cycles (per block) main array block (128 kwords) 100 000 cycles efa block (4 kwords) 100 000 blank check main array block 3.2 ms 1. t a = ?30 to 85 c; v dd = 1.7 v to 2 v; v ddq = 1.7 v to 2 v. 2. values are liable to change with the external system-level overhead (co mmand sequence and status register polling execution). 3. excludes the time needed to execute the command sequence. 4. this is an average value on the entire device. 5. the first word program in a program region will take 115 s, the subsequent words will take 50 s to program. table 22. program/erase times and endurance cycles (1) (2) (continued) parameter condition min typ typical after 100 kw/e cycles max unit
maximum ratings m58pr512le, M58PR001LE 70/123 14 maximum ratings stressing the device above the ratings listed in table 23: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 23. absolute maximum ratings symbol parameter value unit min max t a ambient operating temperature ?30 85 c t bias temperature under bias ?30 85 c t stg storage temperature ?65 125 c v io input or output voltage ?1 3 v v dd supply voltage ?1 3 v v ddq input/output supply voltage ?1 3 v v pp program voltage ?1 10 v i o output short circuit current 100 ma t vpph time for v pp at v pph 100 hours
m58pr512le, M58PR001LE dc and ac parameters 71/123 15 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables in this section are derived from tests performed under the measurement conditions summarized in table 24: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 10. ac measurement i/o waveform table 24. operating and ac measurement conditions parameter min max units v dd supply voltage 1.7 2.0 v v ddq supply voltage 1.7 2.0 v v pp supply voltage (factory environment) 8.5 9.5 v v pp supply voltage (application environment) 0.9 2.0 v ambient operating temperature ?30 85 c load capacitance (c l )30pf input rise and fall times 3 ns input pulse voltages 0 to v ddq v input and output timing ref. voltages v ddq /2 v ai06161 v ddq 0 v v ddq /2
dc and ac parameters m58pr512le, M58PR001LE 72/123 figure 11. ac measurement load circuit table 25. capacitance (1) 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0 v 2 8 pf c out output capacitance v out = 0 v 4 8 pf ai06162 v ddq c l c l includes jig capacitance 16.7 k device under test 0.1 f v dd 0.1 f v ddq 16.7 k
m58pr512le, M58PR001LE dc and ac parameters 73/123 table 26. dc characteristics - currents symbol parameter test condition (1) typ max unit i li input leakage current 0 v v in v ddq 1 a i lo output leakage current 0 v v out v ddq 1 a i dd1 supply current asynchronous read (f=5 mhz) e = v il , g = v ih 25 30 ma supply current page read (f=13 mhz) 510ma supply current synchronous read (f=66 mhz) 8 word 22 27 ma 16 word 19 21 ma continuous 25 29 ma supply current synchronous read (f = 108 mhz) 8 word 26 31 ma 16 word 23 25 ma continuous 30 37 ma i dd2 supply current (reset) rp = v ss 0.2 v 512 mbit 50 160 a 1 gbit 70 255 i dd3 supply current (standby) e = v ddq 0.2 v k = v ss 512 mbit 50 160 a 1 gbit 70 255 i dd4 (1) supply current (automatic standby) e = v il , g = v ih , rp = v ih 512 mbit 50 160 a 1 gbit 70 255 i dd5 (2) supply current (deep power- down) 245a i dd6 (3) supply current (program) v pp = v pph , v pp = v dd 35 50 ma supply current (erase) v pp = v pph , v pp = v dd 35 55 ma supply current (blank check) v pp = v pph , v pp = v dd 35 50 ma i dd7 (3)(4) supply current (dual operations) program/erase in one bank, asynchronous read in another bank 60 85 ma program/erase in one bank, synchronous read (continuous, f = 108 mhz) in another bank 65 92 ma i dd8 (3) supply current program/ erase suspended (standby) e = v ddq 0.2v k = v ss 512 mbit 50 160 a 1 gbit 70 255 i pp1 (3) v pp supply current (program) v pp = v pph 822ma v pp = v dd 0.05 0.1 ma v pp supply current (erase) v pp = v pph 822ma v pp = v dd 0.05 0.1 ma i pp2 v pp supply current (read) v pp v dd 215a
dc and ac parameters m58pr512le, M58PR001LE 74/123 i pp3 (3) v pp supply current (standby, program/erase suspend) v pp v dd 0.2 5 a i pp4 v pp supply current (blank check) v pp = v pph 0.05 0.1 ma v pp = v pp1 0.05 0.1 ma 1. all inputs stable. 2. the dpd current is measured 40 s after entering the deep power-down mode. 3. sampled only, not 100% tested. 4. v dd dual operation current is the sum of read and program or erase currents. table 27. dc characteristics - voltages symbol parameter test condition min typ max unit v il input low voltage 0 0.4 v v ih input high voltage v ddq ?0.4 v ddq + 0.4 v v ol output low voltage i ol = 100 a 0.1 v v oh output high voltage i oh = ?100 a v ddq ?0.1 v v pp1 v pp program voltage-logic program, erase 1.1 1.8 3.3 v v pph v pp program voltage factory program, erase 8.5 9.0 9.5 v v pplk program or erase lockout 0.4 v v lko v dd lock voltage 1 v v rph rp pin extended high voltage 3.3 v v lkoq v ddq lock voltage 0.9 v table 26. dc characteristics - currents (continued) symbol parameter test condition (1) typ max unit
m58pr512le, M58PR001LE dc and ac parameters 75/123 figure 12. asynchronous random access read ac waveforms ai12860b tavav telqx tehqx tglqv tglqx tghqx dq0-dq15 e g telqv tehqz tghqz valid a0-amax (1) valid valid l (2) tellh tllqv tlllh tavlh tlhax taxqx wait (3) teltv tehtz hi-z hi-z tavqv tgltv tghtz notes: 1. amax is equal to a24 in the m58pr512le and to a25 in the M58PR001LE. 2. latch enable, l, can be kept low (also at board level) when the latch enable function is not required or supported. 3. wait is active low.
dc and ac parameters m58pr512le, M58PR001LE 76/123 figure 13. asynchronous page read ac waveforms ai12861c a4-amax (1) e g a0-a3 valid add. l dq0-dq15 valid add. valid add. valid address valid address valid data tlhax tavlh tllqv tavqv1 tglqx tlllh tellh wait (2) tavav telqv telqx teltv tglqv notes: 1. amax is equal to a24 in the m58pr512le and to a25 in the M58PR001LE. 2. wait is active low. valid address latch outputs enabled valid data standby hi-z tgltv valid add. valid add. valid add. valid add. valid data valid data valid data valid data valid data valid data valid data
m58pr512le, M58PR001LE dc and ac parameters 77/123 table 28. asynchronous read ac characteristics symbol alt parameter 108 mhz 66 mhz unit read timings t avav t rc address valid to next address valid min 96 96 ns t avqv t acc address valid to output valid (random) max 96 96 ns t avqv1 t pa g e address valid to output valid (page) max 20 25 ns t axqx (1) 1. sampled only, not 100% tested. t oh address transition to output transition min 0 0 ns t eltv chip enable low to wait valid max 14 14 ns t elqv (2) 2. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv . t ce chip enable low to output valid max 96 96 ns t elqx (1) t lz chip enable low to output transition min 0 0 ns t ehtz chip enable high to wait hi-z max 9 14 ns t ehqx (1) t oh chip enable high to output transition min 0 0 ns t ehqz (1) t hz chip enable high to output hi-z max 9 14 ns t glqv (2) t oe output enable low to output valid max 20 20 ns t glqx (1) t olz output enable low to output transition min 0 0 ns t gltv output enable low to wait valid max 7 11 ns t ghqx (1) t oh output enable high to output transition min 0 0 ns t ghqz (1) t df output enable high to output hi-z max 9 14 ns t ghtz output enable high to wait hi-z max 9 17 ns latch timings t avlh t avadvh address valid to latch enable high min 5 5 ns t ellh t eladvh chip enable low to latch enable high min 9 10 ns t lhax t advhax latch enable high to address transition min 5 5 ns t lllh t advladvh latch enable pulse width min 7 7 ns t llqv t advlqv latch enable low to output valid (random) max 96 96 ns
dc and ac parameters m58pr512le, M58PR001LE 78/123 figure 14. synchronous burst read ac waveforms ai12862b dq0-dq15 e g a0-amax (4) l wait k (3) valid valid valid address tlllh tavlh tglqx tavkh tllkh telkh tkhax tkhqx tkhqv not valid valid note 1 note 2 note 2 tkhtx tehqx tehqz tghqx tghqz hi-z valid note 2 tkhtv tehtz address latch x latency valid data flow boundary crossing valid data standby note 1. the number of clock cycles to be inserted depends on the x latency set in the burst configuration register. 2. the wait signal can be configured to be active during wait state or one cycle before. wait signal is active low. 3. address latched and data output on the rising clock edge. 4. amax is equal to a24 in the m58pr512le and to a25 in the M58PR001LE. tehel tkhqv tkhqx hi-z tgltv
m58pr512le, M58PR001LE dc and ac parameters 79/123 figure 15. single synchronous read ac waveforms figure 16. clock input ac waveform ai12863c e g a0-amax (1) l wait (2,3) k (2) valid address tglqv tavkh tllkh telkh hi-z telqx tkhqv notes: 1. amax is equal to a24 in the m58pr512le and to a25 in the M58PR001LE. 2. the wait signal is configured to be active during wait state. wait signal is active low. 3. address latched and data output on the rising clock edge. tglqx tkhtv dq0-dq15 valid hi-z telqv tgltv tghtz tlltv ai06981 tkhkh tf tr tkhkl tklkh
dc and ac parameters m58pr512le, M58PR001LE 80/123 1. sampled only, not 100% tested. 2. for other timings please refer to table 28: asynchronous r ead ac characteristics . table 29. synchronous read ac characteristics symbol alt parameter 108 mhz 66 mhz unit synchronous read timings t avkh t avclkh address valid to clock high min 5 5 ns t elkh t elclkh chip enable low to clock high min 5 5 ns t ehel chip enable pulse width (subsequent synchronous reads) min 9 11 ns t ehtz chip enable high to wait hi-z max 9 11 ns t khax t clkhax clock high to address transition min 5 5 ns t khqv t khtv t clkhqv clock high to output valid clock high to wait valid max 7 11 ns t khqx t khtx t clkhqx clock high to output transition clock high to wait transition min 2 3 ns t llkh t advlclk h latch enable low to clock high min 5 5 ns t lltv latch enable low to wait valid max 14 14 ns clock specifications t khkh t clk clock period (f=66 mhz) min 15 ns clock period (f=108 mhz) min 9 ns t khkl t klkh clock high to clock low clock low to clock high min 2.5 3.5 ns t f t r clock fall or rise time min 0.3 - ns max 2 3 ns
m58pr512le, M58PR001LE dc and ac parameters 81/123 figure 17. write ac waveforms, write enable controlled e g w dq0-dq15 command cmd or data status register v pp valid address a0-amax (1) tavav tqvvpl tavwh twhax program or erase telwl twheh twhdx tdvwh twlwh twhwl tvphwh set-up command confirm command or data input status register read 1st polling telqv ai12864b twphwh wp twhgl tqvwpl twhel bank address valid address l tavlh tlllh tellh tlhax tghwl twhqv twhwpl twhvpl telkh k twhll twhav note: 1. amax is equal to a24 in the m58pr512le and to a25 in the M58PR001LE
dc and ac parameters m58pr512le, M58PR001LE 82/123 table 30. write ac characteristics, write enable controlled (1) 1. sampled only, not 100% tested. symbol alt parameter 108 mhz 66 mhz unit write enable controlled timings t avav t wc address valid to next address valid min 96 96 ns t avlh address valid to latch enable high min 5 5 ns t avwh (2) address valid to write enable high min 40 40 ns t dvwh t ds data valid to write enable high min 40 40 ns t ellh chip enable low to latch enable high min 9 10 ns t elwl t cs chip enable low to write enable low min 0 0 ns t elqv chip enable low to output valid min 96 96 ns t elkh chip enable low to clock high min 5 5 ns t ghwl output enable high to write enable low min 14 17 ns t lhax latch enable high to address transition min 5 5 ns t lllh latch enable pulse width min 7 7 ns t whav (2) 2. meaningful only if l is always kept low. write enable high to address valid min 0 0 ns t whax (2) t ah write enable high to address transition min 0 0 ns t whdx t dh write enable high to input transition min 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 ns t whel (3) 3. t whel and t whll have this value when reading in the ta rgeted bank or when reading after a set configuration register command. system designers should take this into account and may insert a software no-op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a set confi guration register command. if the first read after the command is a read array operation in a different bank and no changes to the conf iguration register have been issued, t whel is 0 ns. write enable high to chip enable low min 20 20 ns t whgl write enable high to output enable low min 0 0 ns t whll (3) write enable high to latch enable low min 20 20 ns t whwl t wph write enable high to write enable low min 20 20 ns t whqv write enable high to output valid min 116 116 ns t wlwh t wp write enable low to write enable high min 40 40 ns protection timings t qvvpl output (status regi ster) valid to v pp low min 0 0 ns t qvwpl output (status regist er) valid to write protect low min 0 0 ns t vphwh t vps v pp high to write enable high min 200 200 ns t whvpl write enable high to v pp low min 200 200 ns t whwpl write enable high to write protect low min 200 200 ns t wphwh write protect high to write enable high min 200 200 ns
m58pr512le, M58PR001LE dc and ac parameters 83/123 figure 18. write ac waveforms, chip enable controlled w g e dq0-dq15 command cmd or data status register v pp valid address a0-amax (1) tavav tqvvpl taveh tehax program or erase twlel tehwh tehdx tdveh teleh tehel tvpheh set-up command confirm command or data input status register read 1st polling telqv ai12865b twpheh wp tehgl tqvwpl twhel bank address valid address l tavlh tlllh tlhax tghel tehwpl tehvpl telkh k tellh twhqv note: 1. amax is equal to a24 in the m58pr512le and to a25 in the M58PR001LE.
dc and ac parameters m58pr512le, M58PR001LE 84/123 table 31. write ac characteristics, chip enable controlled (1) 1. sampled only, not 100% tested. symbol alt parameter 108 mhz 66 mhz unit chip enable controlled timings t avav t wc address valid to next address valid min 96 96 ns t aveh t wc address valid to chip enable high min 40 45 ns t avlh address valid to latch enable high min 5 5 ns t dveh t ds data valid to chip enable high min 40 40 ns t ehax t ah chip enable high to address transition min 0 0 ns t ehdx t dh chip enable high to input transition min 0 0 ns t ehel t cph chip enable high to chip enable low min 20 20 ns t ehgl chip enable high to output enable low min 0 0 ns t ehwh t ch chip enable high to write enable high min 0 0 ns t elkh chip enable low to clock high min 5 5 ns t eleh t cp chip enable low to chip enable high min 40 45 ns t ellh chip enable low to latch enable high min 9 10 ns t elqv chip enable low to output valid min 96 96 ns t ghel output enable high to chip enable low min 14 17 ns t lhax latch enable high to address transition min 5 5 ns t lllh latch enable pulse width min 7 7 ns t whel (2) 2. t whel has this value when reading in the targeted bank or when reading after a set configuration register command. system designers should take this into acc ount and may insert a software no-op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a set configuration register command. if the first read after the command is a read array operation in a different bank and no changes to the configurati on register have been issued, t whel is 0 ns. write enable high to chip enable low min 20 20 ns t whqv write enable high to output valid min 116 116 ns t wlel t cs write enable low to chip enable low min 0 0 ns protection timings t ehvpl chip enable high to v pp low min 200 200 ns t ehwpl chip enable high to write protect low min 200 200 ns t qvvpl output (status regi ster) valid to v pp low min 0 0 ns t qvwpl output (status regist er) valid to write protect low min 0 0 ns t vpheh t vps v pp high to chip enable high min 200 200 ns t wpheh write protect high to chip enable high min 200 200 ns
m58pr512le, M58PR001LE dc and ac parameters 85/123 figure 19. reset and power-up ac waveforms ai06976 w, rp e, g, vdd, vddq tvdhph tplph power-up reset tplwl tplel tplgl tplll l tphwl tphel tphgl tphll table 32. reset and power-up ac characteristics symbol parameter test condition 108 mhz / 66 mhz unit t plwl t plel t plgl t plll reset low to write enable low, reset low to chip enable low, reset low to output enable low, reset low to latch enable low during program min 25 s during erase min 30 s other conditions min 80 ns t phwl t phel t phgl t phll reset high to write enable low reset high to chip enable low reset high to output enable low reset high to latch enable low min 30 ns t plph (1),(2) rp pulse width min 50 ns t vdhph (3) supply voltages high to reset high min 300 s 1. the device reset is possible but not guaranteed if t plph < 50 ns. 2. sampled only, not 100% tested. 3. it is important to assert rp to allow proper cpu initiali zation during power-up or reset.
dc and ac parameters m58pr512le, M58PR001LE 86/123 figure 20. deep power-down ac waveforms figure 21. reset during deep power-down ac waveforms table 33. deep power-down ac characteristics symbol parameter test condition 108 mhz/66 mhz unit t dpldph deep power-down asserted to deep power-down de-asserted min 50 ns t ehdpl chip enable low to deep power- down asserted min 0 s t dphel deep power-down de-asserted to chip enable low min 75 s t phel reset high to chip enable low during deep power-down min 75 s ai11625 dpd e t ehdpl t dphel t dpldph ai11626 dpd e t ehdpl t phel rp
m58pr512le, M58PR001LE package mechanical 87/123 16 package mechanical to meet environmental requirements, numonyx offers these devices in ecopack? packages. these packages have a lead-free, second-level interconnect. in compliance with jedec standard jesd97, the category of second-level interconnect is marked on the package and on the inner box label. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack specifications are available at: www.numonyx.com . figure 22. tfbga105 9 11 mm - 9 12 active ball array, 0.8 mm pitch, package outline 1. drawing is not to scale. e d eb se a2 a1 a bga-z79 ddd fd d1 e1 e fe ball "a1"
package mechanical m58pr512le, M58PR001LE 88/123 figure 23. tfbga107 8 11 mm - 9 12 active ball array, 0.8 mm pitch, package outline 1. drawing is not to scale. table 34. tfbga105 9 11 mm - 9 12 active ball array, 0.8 mm pitch, mechanical data symbol millimeters inches typ min max typ min max a 1.20 0.047 a1 0.20 0.008 a2 0.80 0.031 b 0.35 0.30 0.40 0.014 0.012 0.016 d 9.00 8.90 9.10 0.354 0.350 0.358 d1 6.40 0.252 ddd 0.10 0.004 e 11.00 10.90 11.10 0.433 0.429 0.437 e1 8.80 0.346 e 0.80 ? ? 0.031 ? ? fd 1.30 0.051 fe 1.10 0.043 se 0.40 0.016 e d eb se a2 a1 a bga-z85 ddd fd d1 e1 e fe ball "b1"
m58pr512le, M58PR001LE package mechanical 89/123 table 35. stacked tfbga107 8 11 mm - 9 12 active ball array, 0.8 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a1.200.047 a1 0.20 0.008 a2 0.85 0.033 b 0.35 0.30 0.40 0.014 0.012 0.016 d 8.00 7.90 8.10 0.315 0.311 0.319 d1 6.40 0.252 ddd 0.10 0.004 e 11.00 10.90 11.10 0.433 0.429 0.437 e1 8.80 0.346 e0.80 0.031 fd 0.80 0.031 fe 1.10 0.043 se 0.40 0.016
part numbering m58pr512le, M58PR001LE 90/123 17 part numbering devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the numonyx sales office nearest to you. table 36. ordering information scheme example: m58pr512l e 96 zad 5 device type m58 architecture p = multilevel, multiple bank, large buffer operating voltage r = v dd = 1.7 v to 2.0 v, v ddq = 1.7 v to 2.0 v density 512 = 512 mbit 001 = 1 gbit technology l = 65 nm technology multilevel design memory organization e = uniform blocks speed 96 = 96 ns package zad = stacked tfbga105 d stacked footprint. zac= stacked tfbga107 c stacked footprint. temperature range 5 = ?30 to 85 c
m58pr512le, M58PR001LE block address tables 91/123 appendix a block address tables the following set of equations can be used to calculate a complete set of block addresses using the information contained in tables 37 , 38 , 39 and 40 . to calculate the block base address from the block number: first it is necessary to calculate the bank number and the block number offset. this can be achieved using the following formulas: for the m58pr512le: bank_number = block_number / 32 block_number_offset = block_number - (bank_number x 32) for the M58PR001LE: bank_number = block_number / 64 block_number_offset = block_number - (bank_number x 64) the block base address is calculated using the formula below: block_base_address = bank_base_address + block_base_address_offset to calculate the bank number and the block number from the block base address: the block number, bank number and block number offset can be calculated using the formulas below: for the m58pr512le: block_number = address / 2 32 bank_number = block_number / 32 block_number_offset = block_number ? (bank_number x 32) for the M58PR001LE: block_number = address / 2 64 bank_number = block_number / 64 block_number_offset = block_number - (bank_number x 64) table 37. m58pr512le - bank base addresses bank number block numbers bank base address 0 0 - 31 0000000 1 32 - 63 0400000 2 64 - 95 0800000 3 96 - 127 0c00000 4 128 - 159 1000000 5 160 - 191 1400000 6 192 - 223 1800000 7 224 - 255 1c00000
block address tables m58pr512le, M58PR001LE 92/123 table 38. M58PR001LE - bank base addresses bank number block numbers bank base address 00 - 630 1 64 - 127 800000 2 128 - 191 1000000 3 192 - 255 1800000 4 256 - 319 2000000 5 320 - 383 2800000 6 384 - 447 3000000 7 448 - 511 3800000
m58pr512le, M58PR001LE block address tables 93/123 table 39. m58pr512le - block addresses block number offset block base address offset 0 0000000 1 0020000 2 0040000 3 0060000 4 0080000 5 00a0000 6 00c0000 7 00e0000 8 0100000 9 0120000 10 0140000 11 0160000 12 0180000 13 01a0000 14 01c0000 15 01e0000 16 0200000 17 0220000 18 0240000 19 0260000 20 0280000 21 02a0000 22 02c0000 23 02e0000 24 0300000 25 0320000 26 0340000 27 0360000 28 0380000 29 03a0000 30 03c0000 31 03e0000
block address tables m58pr512le, M58PR001LE 94/123 table 40. M58PR001LE - block addresses block number block base address offset 0 0000000 1 0020000 2 0040000 3 0060000 4 0080000 5 00a0000 6 00c0000 7 00e0000 8 0100000 9 0120000 10 0140000 11 0160000 12 0180000 13 01a0000 14 01c0000 15 01e0000 16 0200000 17 0220000 18 0240000 19 0260000 20 0280000 21 02a0000 22 02c0000 23 02e0000 24 0300000 25 0320000 26 0340000 27 0360000 28 0380000 29 03a0000 30 03c0000 31 03e0000 32 0400000 33 0420000 34 0440000
m58pr512le, M58PR001LE block address tables 95/123 35 0460000 36 0480000 37 04a0000 38 04c0000 39 04e0000 40 0500000 41 0520000 42 0540000 43 0560000 44 0580000 45 05a0000 46 05c0000 47 05e0000 48 0600000 49 0620000 50 0640000 51 0660000 52 0680000 53 06a0000 54 06c0000 55 06e0000 56 0700000 57 0720000 58 0740000 59 0760000 60 0780000 61 07a0000 62 07c0000 63 07e0000 table 40. M58PR001LE - block addresses (continued) block number block base address offset
common flash interface m58pr512le, M58PR001LE 96/123 appendix b common flash interface the common flash interface is a jedec approved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information, and functions supported by the memory. the system can interface easily with the device, enabling the software to upgrade itself when necessary. when the read cfi query command is issued the device enters cfi query mode and the data structure is read from the memory. tables 41 , 42 , 43 , 44 , 45 , 46 , 47 , 48 , 49 , 50 and 51 show the addresses used to retrieve the data. the query data is always presented on the lowest order data outputs (dq0-dq7), and the other outputs (dq8-dq15) are set to 0. the cfi data structure also contains a security area where a 64-bit unique security number is written (see figure 6: protection register memory map ). this area can only be accessed in read mode by the final user. it is impossible to change the security number after it has been written by st. issue a read array command to return to read mode. table 41. query structure overview (1) 1. the flash memory display the cfi data structure w hen cfi query command is issued. in this table are listed the main sub-sections detailed in tables 42 , 43 , 44 and 45 . query data is always presented on the lowest order data outputs. offset sub-section name description 000h reserved reserved for algorithm-specific information 010h cfi query identification string comma nd set id and algorithm data offset 01bh system interface information device timing and voltage information 027h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) 080h security code area lock protection register unique device number and user programmable otp
m58pr512le, M58PR001LE common flash interface 97/123 table 42. cfi query identification string offset sub-section name description value 000h 0020h manufacturer code st 001h 8819h 880fh device code m58pr512le M58PR001LE 512 mbits 1gbit 002h- 00fh reserved reserved 010h 0051h query unique ascii string "qry" "q" 011h 0052h "r" 012h 0059h "y" 013h 0000h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm 014h 0002h 015h offset = p = 000ah address for primary algorithm extended query table (see ta b l e 4 5 ) p = 10ah 016h 0001h 017h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 018h 0000h 019h value = a = 0000h address for alternate algorithm extended query table na 01ah 0000h
common flash interface m58pr512le, M58PR001LE 98/123 table 43. cfi query system interface information offset data description value 01bh 0017h v dd logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 1.7 v 01ch 0020h v dd logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 2v 01dh 0085h v pp [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 8.5 v 01eh 0095h v pp [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 9.5 v 01fh 0006h typical timeout per single byte/word program = 2 n s 64 s 020h 000bh typical timeout for buffer program = 2 n s 2048 s 021h 000ah typical timeout per individual block erase = 2 n ms 1 s 022h 0000h typical timeout for full chip erase = 2 n ms na 023h 0002h maximum timeout for word program = 2 n times typical 256 s 024h 0002h maximum timeout for buffer program = 2 n times typical 8192 s 025h 0002h maximum timeout per individual block erase = 2 n times typical 4 s 026h 0000h maximum timeout for chip erase = 2 n times typical na
m58pr512le, M58PR001LE common flash interface 99/123 table 44. device geometry definition offset data description value 027h 001ah m58pr512le device size = 2 n in number of bytes 64 mbytes 001bh M58PR001LE device size = 2 n in number of bytes 128 mbytes 028h 029h 0001h 0000h flash device interface code description x16 async. 02ah 02bh 000ah 0000h maximum number of bytes in multi-byte program or page = 2 n 1024 bytes 02ch 0001h number of identical sized erase block regions within the device bit 7 to 0 = x = number of erase block regions 1 02dh 02eh 00ffh 0000h m58pr512le erase block region 1 information number of identical-size erase blocks = 00ffh+1 255 01ffh 0000h M58PR001LE erase block region 1 information number of identical-size erase blocks = 01ffh+1 511 02fh 030h 0000h 0004h erase block region 1 information block size in region 1 = 0400h * 256 byte 256 kbyte 031h 038h reserved reserved for future erase block region information na
common flash interface m58pr512le, M58PR001LE 100/123 table 45. primary algorithm-specific extended query table offset data description value (p)h = 10ah 0050h primary algorithm extended query table unique ascii string ?pri? "p" 0052h "r" 0049h "i" (p+3)h =10dh 0031h major version number, ascii "1" (p+4)h = 10eh 0034h minor version number, ascii "4" (p+5)h = 10fh 00e6h extended query table conten ts for primary algorithm. address (p+5)h contains less significant byte (1 = yes, 0 = no) bit 0 chip erase supported bit 1 erase suspend supported bit 2 program suspend supported bit 3 legacy lock/unlock supported bit 4 queued erase supported bit 5 instant individual block locking supported bit 6 protection bits supported bit 7 page mode read supported bit 8 synchronous read supported bit 9 simultaneous operation supported bit 10 extended flash array blocks supported bit 11 to 29 reserved; undefined bits are ?0?. bit 30 cfi links to follow bit 31 optional features. if bit 31 is ?1? then another 31 bit field of optional features follows at the end of the bit-30 field. no ye s ye s no no ye s ye s ye s ye s ye s ye s no no (p+6)h = 110h 0007h (p+7)h = 111h 0000h (p+8)h = 112h 0000h (p+9)h = 113h 0001h supported functions after suspend read array, read status register and cfi query bit 0 program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1 reserved; undefined bits are ?0? ye s (p+a)h = 114h 0033h block protect status defines which bits in the block status register section of the query are implemented. bit 0 block protect status register lock/unlock bit active (1 = yes, 0 = no) bit 1 block lock status register lock-down bit active (1 = yes, 0 = no) bit 4 efa block protect status register lock/unlock bit active (1=yes, 2=no) bit 5 efa block lock status register lock-down bit active (1=yes, 2=no) bit 15 to 6 and 3 to 2 reserved for future use; undefined bits are ?0? ye s ye s ye s ye s (p+b)h = 115h 0000h (p+c)h = 116h 0018h v dd logic supply optimum program/erase voltage (highest performance) bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 1.8 v (p+d)h = 117h 0090h v pp supply optimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 9v
m58pr512le, M58PR001LE common flash interface 101/123 table 46. protection register information offset data description value (p+e)h = 118h 0002h number of protection register fields in jedec id space. 0000h indicates that 256 fields are available. 2 (p+f)h = 119h 0080h protection field 1: protection description bits 0-7 lower byte of protection register address bits 8-15 upper byte of protection register address bits 16-23 2 n bytes in factory pre-programmed region bits 24-31 2 n bytes in user programmable region 80h (p+10)h = 11ah 0000h 00h (p+ 11)h = 11bh 0003h 8 bytes (p+12)h = 11ch 0003h 8 bytes (p+13)h = 11dh 0089h protection register 2: protection description bits 0-31 protection register address bits 32-39 n number of factory programmed regions (lower byte) bits 40-47 n number of factory programmed regions (upper byte) bits 48-55 2 n bytes in factory programmable region bits 56-63 n number of user programmable regions (lower byte) bits 64-71 n number of user programmable regions (upper byte) bits 72-79 2 n bytes in user programmable region 89h (p+14)h = 11eh 0000h 00h (p+15)h = 11fh 0000h 00h (p+16)h = 120h 0000h 00h (p+17)h = 121h 0000h 0 (p+18)h = 122h 0000h 0 (p+19)h = 123h 0000h 0 (p+1a)h = 124h 0010h 16 (p+1b)h = 125h 0000h 0 (p+1c)h = 126h 0004h 16 table 47. burst read information offset data description value (p+1d)h = 127h 0005h page-mode read capability bits 0-7 ?n? such that 2 n hex value represents the number of read- page bytes. see offset 0028h for device word width to determine page-mode data output width. 32 bytes (p+1e)h = 128h 0003h number of synchronous mode read configuration fields that follow. 3 (p+1f)h = 129h 0002h synchronous mode read capability configuration 1 bit 3-7 reserved bit 0-2 ?n? such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of c ontinuous linear bursts that will output data until the internal burst counter reaches the end of the device?s burstable address space. this field?s 3-bit value can be written directly to the read conf iguration register bit 0-2 if the device is configured for its maximum word width. see offset 0028h for word width to determi ne the burst data output width. 8 (p+20)h = 12ah 0003h synchronous mode read capability configuration 2 16 (p-21)h = 12bh 0007h synchronous mode read capability configuration 3 cont.
common flash interface m58pr512le, M58PR001LE 102/123 table 48. bank and erase block region information offset (1) 1. the variable p is a pointer which is defined at cfi offset 015h. data description (p+22)h = 12ch 01h number of bank regions within the device (2) 2. bank regions. there is one bank region, see tables 37 , 38 , 39 and 40 in appendix a . table 49. bank and erase block region 1 information (1) offset data description (p+23)h = 12dh 16h data size of this bank region information section (addressable locations including this one) (p+24)h = 12eh 00h (p+25)h = 12fh 08h number of identical banks within bank region 1 (p+26)h = 130h 00h (p+27)h = 131h 11h number of program or erase operations allowed in bank region 1: bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+28)h = 132h 00h number of program or erase operatio ns allowed in other banks while a bank in this region is being erased bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+29)h = 133h 00h number of program or erase operatio ns allowed in other banks while a bank in this region is being erased bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+2a)h = 134h 01h types of erase block regions in bank region 1 n = number of erase block regions with contiguous same-size erase blocks. symmetrically blocked banks have one blocking region (2) (p+2b)h = 135h 1fh (3) 3fh (4) bank region 1 erase block type 1 information bits 0-15: n+1 = number of identical-sized erase blocks in each bank bits 16-31: n256 = number of bytes in erase block region (p+2c)h = 136h 00h (p+2d)h = 137h 00h (p+2e)h = 138h 04h (p+2f)h = 139h 64h bank region 1 (erase block type 1) minimum block erase cycles 1000 (p+30)h = 13ah 00h (p+31)h = 13bh 12h bank region 1 (erase block type 1): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved
m58pr512le, M58PR001LE common flash interface 103/123 (p+32)h = 13ch 03h bank region 1 (erase block type 1): page mode and synchronous mode capabilities bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved (p+33)h = 13dh 0ah bank region 1 (erase bl ock type 1) programming region information bit 0-7: aligned size of programming region in bytes bit 8-14: reserved bit 15: legacy flash operation (ignore bit 0-7) bit 16-23: control mode valid size in bytes bit 24-31: reserved bit 32-39: control mode invalid size in bytes bit 40-46: reserved bit 47: legacy flash operation (ignore bit 16-23 and 32-39) (p+34)h = 13eh 00h (p+35)h = 13fh 10h (p+36)h = 140h 00h (p+37)h = 141h 10h (p+38)h = 142h 00h 1. the variable p is a pointer which is defined at cfi offset 015h. 2. bank regions. there is one bank region, see tables 37 , 38 , 39 and 40 in appendix a . 3. applies to m58pr512le. 4. applies to M58PR001LE. table 50. extended flash array bank and erase block region information offset (1) 1. the variable p is a pointer which is defined at cfi offset 015h. data description (p+39)h = 143h 01h number of bank regions within the device (2) 2. bank regions. there is one efa bank region. table 49. bank and erase block region 1 information (1) (continued) offset data description
common flash interface m58pr512le, M58PR001LE 104/123 table 51. extended flash array bank and erase block region 1 information offset (1) data description (p+3a)h = 144h 16h data size of this bank region info rmation section (add ressable locations including this one) (p+3b)h = 145h 00h (p+3c)h = 146h 01h number of identical banks within bank region 1 (p+3d)h = 147h 00h (p+3e)h = 148h 11h number of program or erase operations allowed in bank region 1: bits 0-3: number of simu ltaneous program operations bits 4-7: number of simultaneous erase operations (p+3f)h = 149h 00h number of program or erase operations allowed in other banks while a bank in this region is being erased bits 0-3: number of simu ltaneous program operations bits 4-7: number of simultaneous erase operations (p+40)h = 14ah 00h number of program or erase operations allowed in other banks while a bank in this region is being erased bits 0-3: number of simu ltaneous program operations bits 4-7: number of simultaneous erase operations (p+41)h = 14bh 01h types of erase block regions in bank region 1 n = number of erase block regions with contiguous same-size erase blocks. symmetrically blocked banks have one blocking region (2) . (p+42)h = 14ch 03h bank region 1 erase block type 1 information bits 0-15: n+1 = number of identical-sized erase blocks in each bank bits 16-31: n256 = number of bytes in erase block region (p+43)h = 14dh 00h (p+44)h = 14eh 20h (p+45)h = 14fh 00h (p+46)h = 150h 64h bank region 1 (erase block type 1) minimum block erase cycles 1000 (p+47)h = 151h 00h (p+48)h = 152h 01h bank region 1 (erase block type 1): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for internal ecc used bits 5-7: reserved (p+49)h = 153h 03h bank region 1 (erase block type 1): page mode and synchronous mode capabilities bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved
m58pr512le, M58PR001LE common flash interface 105/123 1. the variable p is a pointer which is defined at cfi offset 015h. 2. bank regions. there is one efa bank region. (p+4a)h = 154h 00h bank region 1 (erase bl ock type 1) programming region information bit 0-7: aligned size of programming region in bytes bit 8-14: reserved bit 15: legacy flash operation (ignore bit 0-7) bit 16-23: control mode valid size in bytes bit 24-31: reserved bit 32-39: control mode invalid size in bytes bit 40-46: reserved bit 47: legacy flash operation (ignore bit 16-23 and 32-39) (p+4b)h = 155h 80h (p+4c)h = 156h 00h (p+4d)h = 157h 00h (p+4e)h = 158h 00h (p+4f)h = 159h 80h table 51. extended flash array bank and erase block region 1 information offset (1) data description
flowcharts and pseudocodes m58pr512le, M58PR001LE 106/123 appendix c flowcharts and pseudocodes figure 24. program and efa block program flowchart and pseudocode 1. any address within the 'a' segment halves (a3=0) in a 1 k byte program region configured in control program mode. if a program command is issued to a pr ogram region configured in the object program mode, sr4 and sr8 are set. 2. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program error) can be made after each program operation or after a sequence. 3. if an error is found, the status register must be cl eared before further program/e rase controller operations. write 41h (main array) or 44h (efa) (1) ai10515 start write address & data read status register (3) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (2, 3) program error (2, 3) program_command (addresstoprogram, datatoprogram) /* efa_program_command (addresstoprogram, datatoprogram) * / { writetoflash (addresstoprogram, 0x41); /*writetoflash (addresstoprogram, 0x44);*/ /* 41h is the command for program array, while 44h is the command for program efa block */ /*see note (1)*/ do { status_register=readflash (addresstoprogram); /* see note (3)*/ /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (2, 3) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
m58pr512le, M58PR001LE flowcharts and pseudocodes 107/123 figure 25. buffer program flowchart and pseudocode 1. n + 1 is the number of data being programmed. the maximum buffer count is 1ff (512 words). 2. next program data is an element belonging to buffer_progr am[].data; next program address is an element belonging to buffer_program[].address. in a program r egion configured in control program mode buffer_program[].data = ffffh if a3 = 1. 3. routine for error check by reading sr3, sr4 and sr1. read status register 70h command, at bank address ai10516b start write buffer data, start address yes x = n end no write n (1) , start address x = 0 write next buffer data, next program address x = x + 1 program buffer to flash confirm d0h read status register no sr7 = 1 yes full status register check (3) (2) no sr7 = 1 yes buffer_program_command (start_address, n, buffer_program[] ) /*the start address must be aligned to a 1kb boundary buffer_program [] is an array structure used to store the address and data to be programmed to the flash memory (the address must be within the segment start address and start address+n) */ { status_register=readflash ( bank _address); } while (status_register.sr7==0); do {writetoflash ( block _address, 0xe9) ; writetoflash ( start _address, n); writetoflash (buffer_program[0].address, buffer_program[0].data); /*buffer_program[0].address is the start address*/ x = 0; while (x flowcharts and pseudocodes m58pr512le, M58PR001LE 108/123 figure 26. program suspend and resume flowchart and pseudocode 1. the read status register command (write 70h) can be issu ed just before or just after the program resume command. write 70h ai10117b read status register yes no sr7 = 1 yes no sr2 = 1 write d0h read data from another address start write b0h program complete write ffh program_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if program has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr2==0) /*program completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_data ( ); /*read data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume program*/ writetoflash (bank_address, 0x70) ; /*read status register to check if program has completed */ } } write ffh program continues with bank in read status register mode read data write 70h (1)
m58pr512le, M58PR001LE flowcharts and pseudocodes 109/123 figure 27. block erase and efa block erase flowchart and pseudocode 1. any address within the bank can equally be used. 2. if an error is found, the status register must be cleared before further program/erase operations. write 20h (main array) or 24h (efa) (1) ai12858 start write block address & d0h read status register (1) yes no sr7 = 1 yes no sr3 = 0 yes sr4, sr5 = 1 v pp invalid error (2) command sequence error (2) no no sr5 = 0 erase error (2) end yes no sr1 = 0 erase to protected block error (2) yes erase_command ( blocktoerase ) /* efa_erase_command (blocktoerase) { */ writetoflash (blocktoerase, 0x20) ; /* writetoflash (blocktoerase, 0x24) */ /* 20h is the command for block erase while 24h is the command for erase efa block*/ /*see note (1) */ writetoflash (blocktoerase, 0xd0) ; /* only a12-amax are significannt */ /* memory enters read status state after the erase command */ } while (status_register.sr7== 0) ; do { status_register=readflash (blocktoerase) ; /* see note (1) */ /* e or g must be toggled*/ if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; if ( (status_register.sr4==1) && (status_register.sr5==1) ) /* command sequence error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; if ( (status_register.sr5==1) ) /* erase error */ error_handler ( ) ; }
flowcharts and pseudocodes m58pr512le, M58PR001LE 110/123 figure 28. erase suspend and resume flowchart and pseudocode 1. the read status register command (write 70h) can be is sued just before or just after the erase resume command. write 70h ai10116c read status register yes no sr7 = 1 yes no sr6 = 1 erase continues with bank in read status register mode write d0h read data from another block or program/set configuration register or block lock/unlock/lock-down start write b0h erase complete write ffh read data write ffh erase_suspend_command ( ) { writetoflash (bank_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if erase has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr6==0) /*erase completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_program_data ( ); /*read or program data from another block*/ writetoflash (bank_address, 0xd0) ; /*write 0xd0 to resume erase*/ writetoflash (bank_address, 0x70) ; /*read status register to check if erase has completed */ } } write 70h (1)
m58pr512le, M58PR001LE flowcharts and pseudocodes 111/123 figure 29. main array and efa locking operations flowchart and pseudocode 1. any address within the bank can equally be used. write 01h, d0h or 2fh ai10518 read block lock states yes no locking change confirmed? start write 60h (main array) or 64h (efa) (1) locking_operation_command (address, lock_operation) { /* efa_locking_operation_command (address, lock_operation) { */ writetoflash (address, 0x60) ; /*configuration setup*/ /* writetoflash (address, 0x64) */ /* 60h is the command for locking operations on the array while 64h is the command for locking operations on the efa */ /* see note (1) */ if (readflash (address) ! = locking_state_expected) error_handler () ; /*check the locking state (see read block signature table )*/ writetoflash (address, 0xff) ; /*reset to read array mode*/ /*see note (1) */ } write ffh (1) write 90h (1) end if (lock_operation==lock) /*to protect the block*/ writetoflash (address, 0x01) ; else if (lock_operation==unlock) /*to unprotect the block*/ writetoflash (address, 0xd0) ; else if (lock_operation==lock-down) /*to lock the block*/ writetoflash (address, 0x2f) ; writetoflash (address, 0x90) ; /*see note (1) */
flowcharts and pseudocodes m58pr512le, M58PR001LE 112/123 figure 30. blank check flowchart and pseudocode 1. any address within the bank can equally be used. 2. if an error is found, the status register must be cleared before further program/erase operations. write block address & bch start sr7 = 1 write block address & d0h read status register (1) sr1 = 0 sr3 = 0 sr4 = 1 sr5 = 1 sr5 = 0 no yes v pp invalid error (2) no command sequence error (2) yes erase error (2) no protected block error (2) no end blank_check_command (blocktocheck) { writetoflash (blocktocheck, 0xbc); writetoflash (blocktocheck, 0xd0); /* memory enters read status state after the blank check command */ do { status_register = readflash (blocktocheck); /* see note (1) */ /* e or g must be toggled */ } while (status_register.sr7==0); if (status_register.sr3==1) /* v pp invalid error */ error_handler () ; if (status_register.sr4==1) && (status_register.sr5==1) /* command sequence error */ error_handler () ; if (status_register.sr5==1) /* erase error */ error_handler () ; if (status_register.sr1==1) /* protected block error */ error_handler () ; } ai10520
m58pr512le, M58PR001LE flowcharts and pseudocodes 113/123 figure 31. protection register program flowchart and pseudocode 1. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cl eared before further program/e rase controller operations. write c0h (1) ai06177c start write address & data read status register (1) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (2, 3) program error (2, 3) protection_register_program_command (addresstoprogram, datatoprogram) {: writetoflash (addresstoprogram, 0xc0) ; /*see note (1) */ do { status_register=readflash (addresstoprogram) ; /* see note (1) */ /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*vpp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (2, 3) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
flowcharts and pseudocodes m58pr512le, M58PR001LE 114/123 figure 32. buffer enhanced factory program flowchart and pseudocode 1. when programming a program region config ured in control program mode, ?b? half segment addresses (a3 = 1) should not contain ?0? values. 2. ba1 = block containing start address wa1. write 80h to address wa1 ai10519b start write d0h to address wa1 write ffffh to address = not ba1 (2) read status register sr7 = 0 no no sr0 = 0 yes read status register sr3 and sr1for errors exit write pdx (1) address wa1 increment count x = x + 1 initialize count x = 0 x = 512 yes read status register last data? yes read status register sr7 = 1 yes full status register check end yes sr4 = 1 no no no no setup phase program and verify phase exit phase buffer_enhanced_factory_program_command (start_address, dataflow[]) { writetoflash (start_address, 0x80) ; writetoflash (start_address, 0xd0) ; do { do { status_register = readflash (start_address); if (status_register.sr4==1) { /*error*/ if (status_register.sr3==1) error_handler ( ) ;/*v pp error */ if (status_register.sr1==1) error_handler ( ) ;/* locked block */ } while (status_register.sr7==1) x=0; /* initialize count */ do { writetoflash (start_address, dataflow[x]); x++; }while (x<512) do { status_register = readflash (start_address); }while (status_register.sr0==1) } while (not last data) writetoflash (another_block_address, ffffh) do { status_register = readflash (start_address) }while (status_register.sr7==0) full_status_register_check(); }
m58pr512le, M58PR001LE command interface state tables 115/123 appendix d command interface state tables table 52. command interface states - modify table, next state 1 command input to chip and resulting chip next state (7) current chip state read array read efa program setup efa program setup bp block erase setup efa block erase setup befp confirm, resume program/ erase suspend read status ffh 94h 41h 44h e9h (8,9,10) 20h 24h 80h d0h b0h 70h ready ready pgrm setup efa block pgrm setup bp setup erase setup efa block erase setup befp setup ready lock/cr/ecr setup ready (sequence error) ready (unlock) ready (sequence error) lock efa block setup otp setup otp busy busy otp busy is in otp busy otp busy is in otp busy otp busy is in otp busy otp busy wp or efa block wp setup wp busy busy program busy is in program busy pgrm busy is in program busy program busy wp suspend wp busy is in program busy wp busy suspend ps is in ps pgrm suspend is in ps program busy wp suspend is in ps wp suspend bp setup (1), (2) bp load 1 (give word count load (n-1)) bp load 1 (2) if n=0 go to bp confirm else go to bp load 2 (data load) (4) bp load 2 (2) bp confirm when count =0 else bp load 2 bp confirm ready (sequence error) bp busy (3) ready (sequence error) bp busy bp busy is in bp busy bp busy is in bp busy bp busy bp suspend bp busy is in bp busy bp busy bp suspend bp suspend is in bp suspend bp suspend is in bp suspend bp busy bp suspend is in bp suspend bp suspend erase or efa block erase setup ready (sequence error) erase busy ready (sequence error) busy erase busy is in erase busy erase busy is in erase busy erase busy es erase busy is in erase busy erase busy suspend es wp setup in es efa block wp in es bp setup in es is in es erase busy es is in es es
command interface state tables m58pr512le, M58PR001LE 116/123 wp in es or efa block wp in es setup wb busy in es busy wp busy in es is in program busy in es wp busy in es is in program busy in es wp busy in es wp suspend is es wp busy in es is in program busy in es wp busy in es suspend wp suspend in es is in ps in es wp suspend in es is in ps in es wp busy in es wp suspend is es is in ps in es wp suspend in es bp in es setup (1) (2) bp load 1 in es (give word count load (n-1)) bp load 1 (2) if n=0 go to bp confirm in es else go to bp load 2 in es (data load) (4) bp load 2 (2) bp confirm in es when count = 0 else bp load 2 in es bp confirm es (sequence error) bp busy in es (3) es (sequence error) bp busy bp busy in es is in bp busy in es bp busy in es is in bp busy in es bp busy in es bp suspend in es bp busy in es is in bp busy in es bp busy in es bp suspend bp suspend in es is in bp suspend in es suspend bp suspend in es is in bp suspend in es bp busy in es bp suspend in es is in bp suspend in es bp suspend in es lock/cr/ecr/lock efa block setup in es es (sequence error) es (unlock block) es (sequence error) blank check setup ready (sequence error) blank check busy ready (sequence error) blank check busy bc busy is in bc busy bc busy is in bc busy bc busy is in blank check busy bc busy befp mode setup ready (sequence error) befp loading data ready (sequence error) befp busy (5) (6) befp program and verify busy (in block address given matches on befp setup command). commands treated as data table 52. command interface states - modify table, next state 1 (continued) command input to chip and resulting chip next state (7) current chip state read array read efa program setup efa program setup bp block erase setup efa block erase setup befp confirm, resume program/ erase suspend read status ffh 94h 41h 44h e9h (8,9,10) 20h 24h 80h d0h b0h 70h
m58pr512le, M58PR001LE command interface state tables 117/123 table 53. command interface states - modify table, next state 2 current chip state command input to chip and resulting chip next state clear sr read id lock, cr, ecr setup lock efa setup blank check setup otp setup block lock confirm lock- down confirm write cr/ecr confirm illegal cmd or befp data wsm operation complete 50h 90h 98h 60h 64h bch c0h 01h 2fh 03h 04h others ready ready lock/cr/e cr setup lock efa block setup blank check setup otp setup ready ready n/a lock/cr/ecr setup ready (sequence error) ready (lock) ready (lock down) ready (set cr) ready (sequence error) lock efa block setup ready (efa lock) ready (sequence error) otp setup otp busy busy otp busy is in otp busy otp busy is ready is in otp busy otp busy wp or efa block wp setup wp busy wp busy n/a busy wp busy is in program busy is wp busy ready is in program busy wp busy is ready suspend wp suspend (error bits cleared) wp suspend is in ps wp suspend n/a is in ps wp suspend bp setup bp load 1 (give word count load (n-1)) n/a bp load 1 if n=0 go to bp confirm else go to bp load 2 (data load) bp load 2 bp confirm when count =0 else bp load 2 bp confirm when count = 0 else bp load 2 bp confirm ready (sequence error) bp busy bp busy is in bp busy is bp busy ready is in bp busy bp busy is ready bp suspend bp suspend (error bits cleared) bp suspend is in bp suspend bp suspend n/a is in bp suspend bp suspend erase or efa block erase setup ready (sequence error) n/a busy erase busy is in erase busy is erase busy ready is in erase busy erase busy is non- ready suspend es (error bits cleared) es lock/cr/e cr setup in es lock efa block setup in es is es n/a is in es es
command interface state tables m58pr512le, M58PR001LE 118/123 wp in es or efa block wp in es setup wp busy in es n/a busy wp busy in es is wp busy in es es is in program busy in es wp busy in es wp busy in es is in es suspend wp suspend is es (error bits cleared) wp suspend in es is in wp suspend in es wp suspend in es n/a is in ps in es wp suspend in es wp suspend in es bp in es setup bp load 1 in es (give word count load (n-1)) n/a bp load 1 if n=0 go to bp confirm in es else go to bp load 2 in es (data load) bp load 2 bp confirm in es when count = 0 else bp load 2 in es bp confirm when count = 0 else bp load 2 bp confirm ready (sequence error) in es bp busy bp busy in es is in bp busy in es is bp busy in es es is in bp busy in es bp busy in es is in es bp suspend bp suspend in es (error bits cleared) bp suspend is es is in bp suspend in es bp suspend in es n/a is in bp suspend in es bp suspend in es bp suspend in es lock/cr/ecr setup in es es (sequence error) es (lock block) es (lock down) es es (lock error) n/a lock efa block setup in es es (sequence error) blank check setup ready (sequence error) ready (error) blank check busy bc busy is in bc busy is bc busy ready is in blank check busy bc busy bc busy is ready befp mode setup ready (sequence error) n/a befp busy befp program and verify busy (in block address given matches on befp setup command). commands treated as data befp busy ready table 53. command interface states - modify table, next state 2 (continued) current chip state command input to chip and resulting chip next state clear sr read id lock, cr, ecr setup lock efa setup blank check setup otp setup block lock confirm lock- down confirm write cr/ecr confirm illegal cmd or befp data wsm operation complete 50h 90h 98h 60h 64h bch c0h 01h 2fh 03h 04h others
m58pr512le, M58PR001LE command interface state tables 119/123 table 54. command interface states - modify table, next output 1 current chip state command input to chip and resulting chip next state read array read efa block wp efa wp bp erase setup efa block erase setup befp setup confirm, resume program/ erase suspend read status ffh 94h 41h 44h e9h 20h 24h 80h d0h b0h 70h befp setup, befp program and verify busy, erase setup, erase efa setup otp setup, bp confirm, wp setup, wp setup in es, bp confirm in es, blank check setup status read efa block wp setup, efa block program setup in es efa block status read lock/cr/ecr setup, lock/cr/ecr setup in es status read efa block lock setup, efa block lock setup in es efa block status read otp busy read array read efa blocks status read efa block status read output state does not change status read efa block status read status read output state does not change status read ready, es, bp suspend, wp busy, erase busy, bp busy, bp busy in es, wp suspend, wp busy in es, ps in es, bp suspend in es, blank check busy bp setup, bp load 1, bp load 2, is output state does not change
command interface state tables m58pr512le, M58PR001LE 120/123 note: 1 wp = word program, bp = buffer program, cmd = command, sr = status register, pgrm = program, is = illegal state, ps = program suspend, es = erase suspend, ci = command interface, cr = configuration register, befp = buffer enhanced factory program, p/e. c. = program/erase controller, wa0 = address in a block different from first befp address, ecr = enhanced configuration register. 2 the output state shows the type of data that appears at the outputs if the bank address is the same as the command address. a bank can be placed in read array, read status register, read electronic signature or read cfi mode, depending on the command issued. each bank remains in its last output state until a new command is issued to that bank. the next state does not depend on the bank output state. 3 at power-up, all banks are in read array mode. issuing a read array command to a busy bank results in undetermined data output. 4 the clear status register command clears the status register error bits except when the p/ec is busy or suspended. 5 befp is allowed only when status register bit sr 0 is reset to ?0?. befp is busy if the block address is the first befp address. any other commands are treated as data. table 55. command interface states - modify table, next output 2 current chip state command input to chip and resulting chip next state clear sr read id lock, cr, ecr setup lock efa setup blank check otp setup lock confirm lock- down confirm write cr/ ecr confirm illegal cmd or befp data 50h 90h 98h 60h 64h bch c0h 01h 2fh 03h 04h others befp setup, befp program and verify busy, erase setup, erase efa setup otp setup, bp confirm, wp setup, wp setup in es, bp confirm in es, blank check setup status read efa block wp setup, efa block program setup in es efa block status read lock/cr/ecr setup, lock/cr/ecr setup in es status read array read status read efa block lock setup, efa block lock setup in es efa block status read array read efa block status read otp busy output state does not change id read status read efa block status read status read output state does not change output state does not change ready, es, bp suspend, wp busy, erase busy, bp busy, blank check busy, bp busy in es, wp suspend, wp busy in es, ps in es, bp suspend in es bp setup, bp load 1, bp load 2, is output state does not change
m58pr512le, M58PR001LE command interface state tables 121/123 6 befp aborts when the block address is different from the first block address and data are ffffh. 7 befp exit when block address is different from first block address and data are ffffh. 8 during bp setup, while entering the number of words to be prog rammed and filling the buffer, the read status of the partition does not change. 9 the bp confirm command changes the read status of the partition to status read. 10 illegal commands are commands not defined in the command set.
revision history m58pr512le, M58PR001LE 122/123 18 revision history table 56. document revision history date revision changes 28-apr-2006 0.1 initial release. 15-may-2006 0.2 1gb density (M58PR001LE part number) added. v pp range for application environment changed in table 24: operating and ac measurement conditions . i pp1 unit changed in table 26: dc characteristics - currents . 14-nov-2006 1 document status promot ed from target specification to preliminary data. address lines modified in figure 13: asynchronous page read ac waveforms . v pp max value modified in table 23: absolute maximum ratings . small text changes. 06-sep-2007 2 modified section 4.18: set enhanced configuration register command and section 4.22: suspend efa block command . updated table 22: program/erase times and endurance cycles , table 23: absolute maximum ratings , table 26: dc characteristics - currents , table 28: asynchronous read ac characteristics , and table 30: write ac characteristics, write enable controlled . added t lltv timing in table 29: synchronous read ac characteristics and figure 15: single synchronous read ac waveforms . modified figure 28: erase suspend and resume flowchart and pseudocode . document status prom oted from preliminary data to datasheet. 19-nov-2007 3 added the tfbga105 (zad) and tfbga107 (zac) packages to the document, most specifically in figure 2: tfbga105 connections (top view through package) , figure 3: tfbga107 connections (top view through package) , figure 22: tfbga105 9 11 mm - 9 12 active ball array, 0.8 mm pitch, package outline , figure 23: tfbga107 8 11 mm - 9 12 active ball array, 0.8 mm pitch, package outline , table 34: tfbga105 9 11 mm - 9 12 active ball array, 0.8 mm pitch, mechanical data , and table 35: stacked tfbga107 8 11 mm - 9 12 active ball array, 0.8 mm pitch, package mechanical data . changed the maximum i dd7 value for ?progr am/erase in one bank, asynchronous read in another bank? from 80 to 85. 21-mar-2008 4 removed the 256 mbit density and all its associated data from the document. applied the numonyx branding. changed all the i dd1 , i dd2 , i dd3 , i dd4 , i dd6 , and i dd8 maximum values in ta bl e 2 6 .
m58pr512le, M58PR001LE 123/123 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties re lating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 11/5/7, numonyx, b.v., all rights reserved.

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